公开(公告)号：US11181971B2

公开(公告)日：2021-11-23

申请号：US16780817

申请日：2020-02-03

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/3296 ,  G06F1/06 ,  G06F1/3206 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/08 ,  G06F1/3237

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

公开(公告)号：US20200174550A1

公开(公告)日：2020-06-04

申请号：US16780817

申请日：2020-02-03

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/3296 ,  G06F13/42 ,  G06F13/40 ,  G06F1/3206 ,  G06F1/06 ,  G06F1/3237 ,  G06F1/08 ,  G06F1/3234

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

公开(公告)号：US09395795B2

公开(公告)日：2016-07-19

申请号：US14032335

申请日：2013-09-20

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/325 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。

公开(公告)号：US10551907B2

公开(公告)日：2020-02-04

申请号：US15184190

申请日：2016-06-16

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/3296 ,  G06F1/06 ,  G06F1/3206 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/08 ,  G06F1/3237

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

公开(公告)号：US20160291685A1

公开(公告)日：2016-10-06

申请号：US15184190

申请日：2016-06-16

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06

CPC classification number: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/325 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

公开(公告)号：US20150089259A1

公开(公告)日：2015-03-26

申请号：US14032335

申请日：2013-09-20

Applicant: Apple Inc.

Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

IPC: G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/325 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。