公开(公告)号：US20200075321A1

公开(公告)日：2020-03-05

申请号：US16552294

申请日：2019-08-27

Applicant: Applied Materials, Inc.

Inventor： Shaunak MUKHERJEE ,  Bo XIE ,  Kevin Michael CHO ,  Kang Sub YIM ,  Deenesh PADHI ,  Astha GARG

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/50

Abstract: Embodiments described herein provide a method of forming a low-k carbon-doped silicon oxide (CDO) layer having a high hardness by a plasma-enhanced chemical vapor deposition (PECVD) process. The method includes providing a carrier gas at a carrier gas flow rate and a CDO precursor at a precursor flow rate to a process chamber. A radio frequency (RF) power is applied at a power level and a frequency to the CDO precursor. The CDO layer is deposited on a substrate within the process chamber.

公开(公告)号：US20200043723A1

公开(公告)日：2020-02-06

申请号：US16515230

申请日：2019-07-18

Applicant: Applied Materials, Inc.

Inventor： Yongjing LIN ,  Tza-Jing GUNG ,  Masaki OGATA ,  Yusheng ZHOU ,  Xinhai HAN ,  Deenesh PADHI ,  Juan Carlos ROCHA ,  Amit Kumar BANSAL ,  Mukund SRINIVASAN

IPC: H01L21/02

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

公开(公告)号：US20190115365A1

公开(公告)日：2019-04-18

申请号：US16151467

申请日：2018-10-04

Applicant: Applied Materials, Inc.

Inventor： Xinhai HAN ,  Deenesh PADHI ,  Er-Xuan PING ,  Srinivas GUGGILLA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US20180350596A1

公开(公告)日：2018-12-06

申请号：US15976945

申请日：2018-05-11

Applicant: Applied Materials, Inc.

Inventor： Milind GADRE ,  Praket P. JHA ,  Deenesh PADHI

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  C23C16/24 ,  C23C16/46 ,  C23C16/509 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/0262

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon (a-Si) layers on a semiconductor substrate. In one implementation, a method is provided. The method comprises generating a pressure within a processing volume between 2 Torr and 60 Torr. The method further comprises heating a substrate in the processing volume to a temperature between 300 degrees Celsius and 550 degrees Celsius. The method further comprises flowing a silane-containing gas mixture into the processing volume having the substrate positioned therein. The method further comprises flowing a borane-containing gas mixture into the processing volume having the substrate positioned therein and depositing a boron-doped amorphous silicon layer on the substrate.

公开(公告)号：US20180315592A1

公开(公告)日：2018-11-01

申请号：US15958747

申请日：2018-04-20

Applicant: Applied Materials, Inc.

Inventor： Xinhai HAN ,  Kang Sub YIM ,  Zhijun JIANG ,  Deenesh PADHI

IPC: H01L21/02 ,  C23C16/40

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

公开(公告)号：US20180076042A1

公开(公告)日：2018-03-15

申请号：US15695269

申请日：2017-09-05

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Ziqing DUAN ,  Milind GADRE ,  Praket P. JHA ,  Abhijit Basu MALLICK ,  Deenesh PADHI

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3105 ,  C23C16/30

CPC classification number: H01L21/28525 ,  C23C16/045 ,  C23C16/24 ,  C23C16/30 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/32055

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.

公开(公告)号：US20170278709A1

公开(公告)日：2017-09-28

申请号：US15602862

申请日：2017-05-23

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Pramit MANNA ,  Li Yan MIAO ,  Deenesh PADHI ,  Bok Hoen KIM ,  Christopher Dennis BENCHER

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L2221/00

Abstract: Embodiments of the disclosure relate to deposition of a conformal organic material over a feature formed in a photoresist or a hardmask, to decrease the critical dimensions and line edge roughness. In various embodiments, an ultra-conformal carbon-based material is deposited over features formed in a high-resolution photoresist. The conformal organic layer formed over the photoresist thus reduces both the critical dimensions and the line edge roughness of the features.

公开(公告)号：US20170170015A1

公开(公告)日：2017-06-15

申请号：US15432605

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Sungjin KIM ,  Deenesh PADHI ,  Sung Hyun HONG ,  Bok Hoen KIM ,  Derek R. WITTY

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.

公开(公告)号：US20170162417A1

公开(公告)日：2017-06-08

申请号：US15370682

申请日：2016-12-06

Applicant: Applied Materials, Inc.

Inventor： Zheng John YE ,  Hiroji HANAWA ,  Juan Carlos ROCHA-ALVAREZ ,  Pramit MANNA ,  Michael Wenyoung TSIANG ,  Allen KO ,  Wenjiao WANG ,  Yongjing LIN ,  Prashant Kumar KULSHRESHTHA ,  Xinhai HAN ,  Bok Hoen KIM ,  Kwangduk Douglas LEE ,  Karthik Thimmavajjula NARASIMHA ,  Ziqing DUAN ,  Deenesh PADHI

IPC: H01L21/683 ,  C23C16/505 ,  C23C16/458

CPC classification number: H01L21/6833 ,  C23C16/4586 ,  C23C16/509 ,  H01J37/32091 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556

Abstract: Techniques are disclosed for methods and apparatuses of an electrostatic chuck suitable for operating at high operating temperatures. In one example, a substrate support assembly is provided. The substrate support assembly includes a substantially disk-shaped ceramic body having an upper surface, a cylindrical sidewall, and a lower surface. The upper surface is configured to support a substrate thereon for processing the substrate in a vacuum processing chamber. The cylindrical sidewall defines an outer diameter of the ceramic body. The lower surface is disposed opposite the upper surface. An electrode is disposed in the ceramic body. A circuit is electrically connected to the electrode. The circuit includes a DC chucking circuit, a first RF drive circuit, and a second RF dive circuit. The DC chucking circuit, the first RF drive circuit and the second RF drive circuit are electrically coupled with the electrode.

公开(公告)号：US20160172239A1

公开(公告)日：2016-06-16

申请号：US14943913

申请日：2015-11-17

Applicant: Applied Materials, Inc.

Inventor： Deenesh PADHI ,  Yihong CHEN ,  Kelvin CHAN ,  Abhijit Basu MALLICK ,  Alexandros T. DEMOS ,  Mukund SRINIVASAN

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5329 ,  C23C16/30 ,  C23C16/452 ,  C23C16/45523 ,  H01L21/0214 ,  H01L21/02145 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Implementations described herein generally relate to the formation of a silicon and aluminum containing layer. Methods described herein can include positioning a substrate in a process region of a process chamber; delivering a process gas to the process region, the process gas comprising an aluminum-containing gas and a silicon-containing gas; activating a reactant gas comprising a nitrogen-containing gas, a hydrogen containing gas, or combinations thereof; delivering the reactant gas to the process gas to create a deposition gas that deposits a silicon and aluminum containing layer on the substrate; and purging the process region. The above elements can be performed one or more times to deposit an etch stop stack.

Abstract translation: 本文描述的实施方案一般涉及形成含硅和铝的层。 本文所述的方法可以包括将基底定位在处理室的处理区域中; 将工艺气体输送到所述工艺区域，所述工艺气体包括含铝气体和含硅气体; 活化包含含氮气体，含氢气体或其组合的反应气体; 将反应气体输送到工艺气体以产生在衬底上沉积含硅和铝的层的沉积气体; 并清除过程区域。 可以执行上述元件一次或多次以沉积蚀刻停止叠层。