公开(公告)号：US10014174B2

公开(公告)日：2018-07-03

申请号：US15602862

申请日：2017-05-23

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Pramit Manna ,  Li Yan Miao ,  Deenesh Padhi ,  Bok Hoen Kim ,  Christopher Dennis Bencher

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L2221/00

Abstract: Embodiments of the disclosure relate to deposition of a conformal organic material over a feature formed in a photoresist or a hardmask, to decrease the critical dimensions and line edge roughness. In various embodiments, an ultra-conformal carbon-based material is deposited over features formed in a high-resolution photoresist. The conformal organic layer formed over the photoresist thus reduces both the critical dimensions and the line edge roughness of the features.

公开(公告)号：US09631278B2

公开(公告)日：2017-04-25

申请号：US14919196

申请日：2015-10-21

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  David Thompson

IPC: C23C16/00 ,  C23C16/56 ,  C23C16/18 ,  C23C16/42

CPC classification number: C23C16/56 ,  C23C16/18 ,  C23C16/42

Abstract: Methods for depositing or forming a metal silicide layer are disclosed. A metal halide layer is deposited, cleaned by a halogen and subjected to a siliciding agent to form the metal silicide.

公开(公告)号：US09613859B2

公开(公告)日：2017-04-04

申请号：US14975231

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Annamalai Lakshmanan ,  Bencherki Mebarki ,  Kaushal K. Singh ,  Paul F. Ma ,  Mehul B. Naik ,  Andrew Cockburn ,  Ludovic Godet

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L23/53271 ,  H01L2221/1094

Abstract: Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.

公开(公告)号：US09337051B2

公开(公告)日：2016-05-10

申请号：US14799374

申请日：2015-07-14

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Bok Hoen Kim ,  Deenesh Padhi ,  Li Yan Miao ,  Pramit Manna ,  Christopher Dennis Bencher ,  Mehul B. Naik ,  Huixiong Dai ,  Christopher S. Ngai ,  Daniel Lee Diehl

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/3088 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144

Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Abstract translation: 本公开的实施例通常提供在与上覆光致抗蚀剂层光学匹配的硬掩模中形成减小尺寸图案的方法。 该方法通常包括在低于光致抗蚀剂的分解温度的温度下，在图案化的光致抗蚀剂和下面的硬掩模的场区域，侧壁和底部上施加尺寸收缩的保形碳层。 本文的方法和实施例还涉及通过蚀刻工艺从图案化的光致抗蚀剂和硬掩模的底部部分去除保形碳层，以暴露硬掩模，在底部蚀刻暴露的硬掩模基板，随后同时去除 保形碳层，光致抗蚀剂等碳质成分。 因此产生了用于进一步模式转移的尺寸减小特征的硬掩模。

公开(公告)号：US11776805B2

公开(公告)日：2023-10-03

申请号：US17197475

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Joung Joo Lee ,  Yi Xu ,  Yu Lei ,  Xianmin Tang ,  Kelvin Chan ,  Alexander Jansen ,  Philip A. Kraus

IPC: H01L21/02 ,  H01L21/30

CPC classification number: H01L21/0206 ,  H01L21/02068 ,  H01L21/3003

Abstract: Method for selectively oxidizing the dielectric surface of a substrate surface comprising a dielectric surface and a metal surface are discussed. Method for cleaning a substrate surface comprising a dielectric surface and a metal surface are also discussed. The disclosed methods oxidize the dielectric surface and/or clean the substrate surface using a plasma generated from hydrogen gas and oxygen gas. The disclosed method may be performed in a single step without the use of separate competing oxidation and reduction reactions. The disclosed methods may be performed at a constant temperature and/or within a single processing chamber.

公开(公告)号：US11189710B2

公开(公告)日：2021-11-30

申请号：US16874889

申请日：2020-05-15

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Tejinder Singh ,  Bencherki Mebarki

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/033 ,  H01L29/786

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

公开(公告)号：US11170982B2

公开(公告)日：2021-11-09

申请号：US16529211

申请日：2019-08-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Anantha K. Subramani ,  Praburam Raja ,  Steven V. Sansoni ,  John Forster ,  Philip Kraus ,  Yang Guo ,  Prashanth Kothnur ,  Farzad Houshmand ,  Bencherki Mebarki ,  John Joseph Mazzocco ,  Thomas Brezoczky

IPC: H01J37/34 ,  B08B7/00 ,  H01L21/033

Abstract: Methods and apparatus for low angle, selective plasma deposition on a substrate. A plasma chamber uses a process chamber having an inner processing volume, a three dimensional (3D) magnetron with a sputtering target with a hollow inner area that overlaps at least a portion of sides of the sputtering target and moves in a linear motion over a length of the sputtering target, a housing surrounding the 3D magnetron and the sputtering target such that at least one side of the housing exposes the hollow inner area of the sputtering target, and a linear channel interposed between the housing and a wall of the process chamber.

公开(公告)号：US20210287898A1

公开(公告)日：2021-09-16

申请号：US17197475

申请日：2021-03-10

Applicant: Applied Materials, Inc

Inventor： Bencherki Mebarki ,  Joung Joo Lee ,  Yi Xu ,  Yu Lei ,  Xianmin Tang ,  Kelvin Chan ,  Alexander Jansen ,  Philip A. Kraus

IPC: H01L21/02 ,  H01L21/30

Abstract: Method for selectively oxidizing the dielectric surface of a substrate surface comprising a dielectric surface and a metal surface are discussed. Method for cleaning a substrate surface comprising a dielectric surface and a metal surface are also discussed. The disclosed methods oxidize the dielectric surface and/or clean the substrate surface using a plasma generated from hydrogen gas and oxygen gas. The disclosed method may be performed in a single step without the use of separate competing oxidation and reduction reactions. The disclosed methods may be performed at a constant temperature and/or within a single processing chamber.

公开(公告)号：US20200373411A1

公开(公告)日：2020-11-26

申请号：US16874889

申请日：2020-05-15

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Tejinder Singh ,  Bencherki Mebarki

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/423 ,  H01L21/02

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

公开(公告)号：US20190287772A1

公开(公告)日：2019-09-19

申请号：US16351651

申请日：2019-03-13

Applicant: APPLIED MATERIALS, INC.

Inventor： JOUNG JOO LEE ,  Bencherki Mebarki ,  Xianmin Tang ,  KEITH MILLER ,  SREE RANGASAI KESAPRAGADA ,  Sudarsan Srinivasan

IPC: H01J37/34 ,  C23C14/54 ,  H01L21/02

Abstract: Methods and apparatus for physical vapor deposition (PVD) are provided herein. In some embodiments, a method for PVD includes providing a first stream of a first material from a first PVD source towards a surface of a substrate at a first non-perpendicular angle to the plane of the substrate surface and rotating and linearly scanning the substrate through the stream of first material to deposit the first material on all features formed on the substrate, providing a second stream of an ionized dopant species from a dopant source towards the surface of the substrate at a second non-perpendicular angle to the plane of the substrate surface, and implanting the ionized dopant species in the first material deposited only on a top portion and a portion of the first and second sidewalls of all the features on the substrate by rotating and linearly scanning the substrate via the substrate support.