公开(公告)号：US06777325B2

公开(公告)日：2004-08-17

申请号：US10414010

申请日：2003-04-16

申请人： Daisuke Ryuzaki ,  Takeshi Furusawa

发明人： Daisuke Ryuzaki ,  Takeshi Furusawa

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3143 ,  H01L21/3148 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/7684

摘要： Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.

摘要翻译： 公开了具有叠层结构的电介质膜的半导体器件，包括含有硅，氧和碳的低介电常数膜，用于含有硅，氧，碳和氟的低介电常数膜的改性层和相继形成的介电保护膜 在半导体衬底上，半导体器件是通过使用含氟气体的等离子体处理施加到有机硅氧烷膜的表面上以形成改性层，然后形成电介质保护膜来制造的，这可以改善与电介质的粘附性 保护膜不增加有机硅氧烷膜的介电常数，防止分层。

公开(公告)号：US08487192B2

公开(公告)日：2013-07-16

申请号：US12946993

申请日：2010-11-16

申请人： Masatoshi Kunieda ,  Kazuhiro Yoshikawa ,  Takeshi Furusawa

发明人： Masatoshi Kunieda ,  Kazuhiro Yoshikawa ,  Takeshi Furusawa

IPC分类号： H05K3/02 ,  H05K3/10 ,  H05K1/03

CPC分类号： H01L23/49861 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/205 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.

摘要翻译： 一种印刷电路板，包括由树脂材料制成并具有第一和第二表面的绝缘层，所述绝缘层具有在第二表面上开口的开口部分，具有第一和第二表面的导电电路，所述导电电路嵌入绝缘体中 使得导电电路的第一表面与绝缘层的第一表面齐平并且导电电路的第二表面通过绝缘层的开口部露出，形成在第一表面处理膜上的第一表面处理膜 导电电路并且面对导电电路的第一表面，以及形成在导电电路上并面向导电电路的第二表面和绝缘层的开口部分的第二表面处理膜。

公开(公告)号：US20120289032A1

公开(公告)日：2012-11-15

申请号：US13476471

申请日：2012-05-21

申请人： Takeshi FURUSAWA ,  Takao KAMOSHIMA ,  Masatsugu AMISHIRO ,  Naohito SUZUMURA ,  Shoichi FUKUI ,  Masakazu OKADA

发明人： Takeshi FURUSAWA ,  Takao KAMOSHIMA ,  Masatsugu AMISHIRO ,  Naohito SUZUMURA ,  Shoichi FUKUI ,  Masakazu OKADA

IPC分类号： H01L21/20

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11, insulating films 14, 15, 16 are formed. An opening is formed in those insulating films and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 to form the opening. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance. By interposing the insulating film 14 therebetween with a higher density of Si (silicon) atoms than the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中形成MISFET。 在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在绝缘膜11上形成绝缘膜14,15,16。 在这些绝缘膜中形成开口，并且在其中嵌入线。 当蚀刻绝缘膜16以形成开口时，绝缘膜15是蚀刻停止膜。 绝缘膜11具有高吸湿性，绝缘膜15具有低的耐湿性。 通过在绝缘膜14之间插入比绝缘膜11高的Si（硅）原子密度，可以防止形成电性弱的界面。

公开(公告)号：US20120199389A1

公开(公告)日：2012-08-09

申请号：US13442921

申请日：2012-04-10

申请人： Toshiki FURUTANI ,  Takeshi Furusawa

发明人： Toshiki FURUTANI ,  Takeshi Furusawa

IPC分类号： H05K1/11

CPC分类号： H05K1/113 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K3/428 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0542 ,  H05K2203/166 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.

摘要翻译： 一种制造印刷线路板的方法，其中形成了具有减少连接故障的填充过孔，并且提供了这种印刷线路板。 在通孔开口的内壁上形成无电镀膜后，对绝缘性树脂基材进行电解电镀; 通孔开口填充有电镀金属，并形成填充的通孔。 因此，在电解电镀期间，电化学金属由通孔开口的侧壁以及通孔开口的底部的无电镀膜沉积。 结果，通孔开口可以通过电解电镀完全填充，形成填充的通孔，同时减少连接错误。

公开(公告)号：US08203210B2

公开(公告)日：2012-06-19

申请号：US12883031

申请日：2010-09-15

申请人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US20110139498A1

公开(公告)日：2011-06-16

申请号：US12946993

申请日：2010-11-16

申请人： Masatoshi Kunieda ,  Kazuhiro Yoshikawa ,  Takeshi Furusawa

发明人： Masatoshi Kunieda ,  Kazuhiro Yoshikawa ,  Takeshi Furusawa

IPC分类号： H05K1/09 ,  H05K1/00 ,  H05K3/00

CPC分类号： H01L23/49861 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/205 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A printed wiring board including an insulation layer made of a resin material and having first and second surfaces, the insulation layer having an opening portion opened on the second surface, a conductive circuit having first and second surfaces, the conductive circuit being embedded in the insulation layer such that the first surface of the conductive circuit is formed flush with the first surface of the insulation layer and that the second surface of the conductive circuit is exposed through the opening portion of the insulation layer, a first surface-treatment film formed on the conductive circuit and facing the first surface of the conductive circuit, and a second surface-treatment film formed on the conductive circuit and facing the second surface of the conductive circuit and in the opening portion of the insulation layer.

摘要翻译： 一种印刷电路板，包括由树脂材料制成并具有第一和第二表面的绝缘层，所述绝缘层具有在第二表面上开口的开口部分，具有第一和第二表面的导电电路，所述导电电路嵌入绝缘体中 使得导电电路的第一表面与绝缘层的第一表面齐平并且导电电路的第二表面通过绝缘层的开口部露出，形成在第一表面处理膜上的第一表面处理膜 导电电路并且面对导电电路的第一表面，以及形成在导电电路上并面向导电电路的第二表面和绝缘层的开口部分的第二表面处理膜。

公开(公告)号：US20100327449A1

公开(公告)日：2010-12-30

申请号：US12880520

申请日：2010-09-13

申请人： Takeshi FURUSAWA ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

发明人： Takeshi FURUSAWA ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。

公开(公告)号：US20100314620A1

公开(公告)日：2010-12-16

申请号：US12794739

申请日：2010-06-05

申请人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Hiroki Takewaka

发明人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Hiroki Takewaka

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L21/768 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

摘要： To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film.

摘要翻译： 抑制或防止在外部端子下面的绝缘膜中产生裂纹，该绝缘膜可能由于加到半导体器件的外部端子上的外力引起。 形成在硅衬底的主表面上的布线层的顶部布线层MH具有包括含有铝的导体图案的衬垫。 在焊盘的下表面上，设置有由第一阻挡导体膜和第二阻挡导体膜从下方层叠形成的阻挡导体膜。 在比顶部布线层低一层的第五布线层中，在与平面中的焊盘的探针接触区域重叠的区域中，不布置导体图案。 此外，第一和第二阻挡导体膜分别是包括钛和氮化钛作为主要成分的导体膜。 此外，第一阻挡导体膜比第二阻挡导体膜厚。

公开(公告)号：US20100236822A1

公开(公告)日：2010-09-23

申请号：US12498860

申请日：2009-07-07

申请人： Toshiki FURUTANI ,  Takeshi FURUSAWA

发明人： Toshiki FURUTANI ,  Takeshi FURUSAWA

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/244 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2224/0401

摘要： A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed.

摘要翻译： 布线板形成有基板，在基板的厚度方向上层叠的导电图案，具有预定间距的多个焊盘，并形成在与导电图案相同的层上，布置在多个焊盘的每一个上的导电接合层，以及 具有电极的电子部件。 这里，电子部件配置在基板的内部。 电子部件的电极和多个焊盘通过接合层彼此电连接。 此外，多个焊盘中的每一个的高度大于与每个焊盘相邻的导电图案的高度。 此外，至少在形成焊盘和第一导电图案的层上形成与结合层相关的保护材料。

公开(公告)号：US20100151673A1

公开(公告)日：2010-06-17

申请号：US12714039

申请日：2010-02-26

申请人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

发明人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.