公开(公告)号：US20230343818A1

公开(公告)日：2023-10-26

申请号：US17811105

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Shin-Hung Tsai ,  Cheng-Hao Hou ,  Te-Yang Lai ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L49/02 ,  H01L23/522 ,  C23C16/40 ,  C23C16/455 ,  C23C8/12 ,  C23C16/06

CPC classification number: H01L28/91 ,  H01L23/5223 ,  C23C16/403 ,  C23C16/45525 ,  C23C8/12 ,  C23C16/06

Abstract: A method includes forming a capacitor, which includes forming a first capacitor electrode, forming a first capacitor insulator over the first capacitor electrode, and forming a second capacitor electrode over and contacting the first capacitor insulator. The formation of the first capacitor insulator includes oxidizing a top surface layer of the first capacitor electrode to form a metal oxide layer on the first capacitor electrode, depositing an aluminum oxide layer through a first ALD process having a first plurality of ALD cycles, with the first plurality of ALD cycles having a first ALD cycle number, and depositing a high-k dielectric layer over the aluminum oxide layer. The high-k dielectric layer is deposited through a second ALD process having a second ALD cycle number different from the first ALD cycle number.

公开(公告)号：US11764292B2

公开(公告)日：2023-09-19

申请号：US17699994

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US11764221B2

公开(公告)日：2023-09-19

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US11758736B2

公开(公告)日：2023-09-12

申请号：US17674422

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/15 ,  H10B53/20 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

CPC classification number: H10B53/20 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes: forming a first fin protruding above a substrate; forming first source/drain regions over the first fin; forming a first plurality of nanostructures over the first fin between the first source/drain regions; forming a first gate structure around the first plurality of nanostructures; and forming a first ferroelectric capacitor over and electrically coupled to the first gate structure.

公开(公告)号：US11757020B2

公开(公告)日：2023-09-12

申请号：US16941445

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/385 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7851 ,  H01L21/385 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/785

Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

公开(公告)号：US20230282725A1

公开(公告)日：2023-09-07

申请号：US18316419

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4908 ,  H01L29/66742 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L27/092

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

公开(公告)号：US20230275140A1

公开(公告)日：2023-08-31

申请号：US18303841

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L29/66553 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/0259 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

公开(公告)号：US20230275094A1

公开(公告)日：2023-08-31

申请号：US18312742

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/41791 ,  H01L21/823475 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76843

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

公开(公告)号：US20230261045A1

公开(公告)日：2023-08-17

申请号：US17739259

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices including air gaps between source/drain regions and a semiconductor substrate and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source/drain region adjacent the gate structure and the first channel region; a first inner spacer layer between the first source/drain region and the semiconductor substrate in a first direction perpendicular to a major surface of the semiconductor substrate; and a first air gap between the first source/drain region and the first inner spacer layer in the first direction.

公开(公告)号：US11727976B2

公开(公告)日：2023-08-15

申请号：US17814755

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L29/51 ,  G11C11/22

CPC classification number: G11C11/221 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.