-
公开(公告)号：US11764762B1
公开(公告)日：2023-09-19
申请号：US17898332
申请日：2022-08-29
发明人： Haoyu Xiong , Min Chen
IPC分类号： H03K3/03 , H03K19/0944 , H03K3/354
CPC分类号： H03K3/0315 , H03K3/354 , H03K19/0944
摘要： An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.
-
公开(公告)号：US11750202B2
公开(公告)日：2023-09-05
申请号：US17683016
申请日：2022-02-28
申请人： Kioxia Corporation
发明人： Takayuki Tsukamoto
IPC分类号： H03L7/099 , H03K3/03 , H03K5/151 , H03K17/687 , G11C11/4074 , H03L7/18
CPC分类号： H03L7/0995 , G11C11/4074 , H03K3/0315 , H03K5/151 , H03K17/687 , H03L7/18
摘要： A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.
-
公开(公告)号：US11742868B1
公开(公告)日：2023-08-29
申请号：US17677724
申请日：2022-02-22
发明人： Eric A. Becker , Tyler J. Gomm
CPC分类号： H03M1/0617 , G04F10/005 , H03K3/0315 , H03M7/165
摘要： A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.
-
24.发明授权公开(公告)号：US11742837B2
公开(公告)日：2023-08-29
申请号：US17421688
申请日：2021-05-13
发明人： Dongmyung Lee , Donghoon Baek , Jangjin Nam
CPC分类号： H03K3/0322 , H03L7/0995 , H03K5/00
摘要： This disclosure provides a voltage controlled oscillator and a control method thereof, a P2P interface circuit, an electronic device, and relates to the field of voltage controlled oscillation technology. The voltage controlled oscillator includes N stages of delay units, and the delay unit of each stage includes: a first inverter, a second inverter, a third inverter, and a fourth inverter; both the second inverter and the third inverter are electrically connected to a frequency control terminal, and whether to activate the second inverter and the third inverter is controlled by the frequency control terminal.
-
公开(公告)号：US11728771B2
公开(公告)日：2023-08-15
申请号：US17732902
申请日：2022-04-29
发明人： Kohei Beppu , Takehiro Yamamoto
摘要： A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.
-
公开(公告)号：US20230253959A1
公开(公告)日：2023-08-10
申请号：US18010234
申请日：2021-06-17
发明人： Alon Cervera
CPC分类号： H03K3/0315 , H03K5/22 , H03K5/14 , H03K2005/00078
摘要： A high-resolution adaptive digital frequency synthesizer Integrated Circuit (IC) for wireless power systems, which comprises a digitally controlled tunable ring-oscillator, based on a chain of delay-line cells (DLs) being adapted to generate an internal high-resolution reference clock signal; a tuner unit for receiving as input a compensation/target signal and performing arithmetic operations that produce auxiliary tuning signals provided to the ring-oscillator, for allowing the ring-oscillator to generate a high-resolution output period/frequency; a counter-comparator unit introducing an additional delay to the chain, the counter-comparator unit operating in combination with the ring-oscillator and counts how many times the delay of the chain repeats, for providing ultra-fine tuning signal for tuning the frequency resolution of digitally controlled ring-oscillator; an adaptive Fractional-N dithering module, for enhancing the frequency resolution of the digitally controlled ring-oscillator by averaging the resolution provided by a single delay-line cell of the ring-oscillator.
-
27.发明授权公开(公告)号：US11705897B2
公开(公告)日：2023-07-18
申请号：US17495608
申请日：2021-10-06
发明人： Xu Zhang , Xuhao Huang , Shitong Zhao
CPC分类号： H03K5/14 , G05F1/56 , H03F3/45475 , H03K3/0315 , H04B1/40
摘要： An aspect relates to an apparatus, including: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.
-
公开(公告)号：US11671103B2
公开(公告)日：2023-06-06
申请号：US17571228
申请日：2022-01-07
申请人： Apple Inc.
发明人： Ramy A. Ahmed , Bruno W. Garlepp , Jafar Savoj
IPC分类号： H03K21/00 , H03K21/40 , H03K3/03 , H03K19/0175 , H03K21/08
CPC分类号： H03K21/403 , H03K3/0315 , H03K19/017509 , H03K21/08
摘要： A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.
-
公开(公告)号：US11671078B2
公开(公告)日：2023-06-06
申请号：US17520063
申请日：2021-11-05
发明人： Bruno Gailhard
CPC分类号： H03K3/0315 , G06F1/06 , G06F1/08 , H03K5/00006 , H03K5/26 , H03L7/093 , H03L7/0995
摘要： A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.
-
公开(公告)号：US20230171114A1
公开(公告)日：2023-06-01
申请号：US17537605
申请日：2021-11-30
发明人： Dallas Lea , Yann Mignot , Marc A. Bergendahl , Alex Joseph Varghese , Sean Teehan , Andrew M. Greene , Matthew T. Shoudy
CPC分类号： H04L9/3278 , H03K3/0315 , H03H7/06 , H03H7/0161 , H03K3/037
摘要： A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.
-
-
-
-
-
-
-
-
-
搜索结果
2549 条记录 (耗时 0.028 秒)
