Ring oscillator with stages implemented to assess PFET-NFET process performance

    公开(公告)号:US11764762B1

    公开(公告)日:2023-09-19

    申请号:US17898332

    申请日:2022-08-29

    CPC classification number: H03K3/0315 H03K3/354 H03K19/0944

    Abstract: An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.

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