公开(公告)号：US4453249A

公开(公告)日：1984-06-05

申请号：US347135

申请日：1982-02-09

Applicant: Dieter Roth ,  Herbert Schorb ,  Herbert Kloss

Inventor： Dieter Roth ,  Herbert Schorb ,  Herbert Kloss

IPC: H04L1/00 ,  H04L1/10 ,  G06F11/10

CPC classification number: H04L1/0057 ,  H04L1/0041 ,  H04L1/0045

Abstract: A binary data transmission system uses a code consisting of n-bit code words of a quasi-cyclic code with k information bits and n-k check bits. An encoder and a decoder with an error-detection and -correction facility are provided which use a quasi-cyclic code that has a high error-correcting capacity and requires little storage space.

Abstract translation: 二进制数据传输系统使用由具有k个信息比特和n-k个校验比特的准循环码的n比特码字组成的码。 提供了具有错误检测和校正设施的编码器和解码器，其使用具有高纠错能力并且需要很少的存储空间的准循环码。

公开(公告)号：US4035766A

公开(公告)日：1977-07-12

申请号：US601145

申请日：1975-08-01

Applicant: William B. Barker

Inventor： William B. Barker

IPC: G06F11/10 ,  G11C29/00 ,  H04L1/10

CPC classification number: G06F11/10

Abstract: The error-checking scheme disclosed herein is adapted for use in digital data processing systems, e.g. computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address. In a preferred embodiment, the data is divided into two fields and a respective parity bit is generated corresponding to each data field. Each data parity bit is then combined with a parity bit corresponding to the binary address to yield a respective combinational parity bit. Each of the resultant combinational parity bits is then sourced with the respective data field. Accordingly, a system sub-component receiving the sourced data with the combinational parity bits can detect any type of single error occurring in either the address or the data.

Abstract translation: 本文公开的错误检查方案适用于数字数据处理系统，例如， 计算机，其中二进制数据被不同地发送和/或存储，并且数据源或目的地由二进制地址指定。 在优选实施例中，数据被分成两个字段，并且对应于每个数据字段生成相应的奇偶校验位。 然后将每个数据奇偶校验位与对应于二进制地址的奇偶校验位组合，以产生相应的组合奇偶校验位。 所得到的组合奇偶校验位中的每一个然后用相应的数据字段来源。 因此，接收具有组合奇偶校验位的源数据的系统子组件可以检测在地址或数据中发生的任何类型的单个错误。

公开(公告)号：US3978407A

公开(公告)日：1976-08-31

申请号：US598244

申请日：1975-07-23

Applicant: George D. Forney, Jr. ,  James C. Hart

Inventor： George D. Forney, Jr. ,  James C. Hart

IPC: H03H15/00 ,  H04B1/06 ,  H04B3/10 ,  H04J99/00 ,  H04L25/03 ,  H04L27/00 ,  H04L27/38 ,  H04L1/10

CPC classification number: H04L25/03044 ,  H04L25/0305 ,  H04L27/38

Abstract: Initial Adjustment of a receiver having an automatic adaptive equalizer in a modem communication system is accomplished by employing a data transmission rate lower than normal for an early segment of each burst of signals. At this lower rate, accurate reception is possible without complete adaptation of the equalizer. These same (early segment) signals are used to adapt the equalizer in a decision-directed mode. When the adaptation is completed the system switches to its normal higher rate of data transmission.

公开(公告)号：US3978406A

公开(公告)日：1976-08-31

申请号：US603901

申请日：1975-08-11

Applicant: Youichi Matsumoto ,  Seijiro Yokoyama ,  Tadao Shimamura

Inventor： Youichi Matsumoto ,  Seijiro Yokoyama ,  Tadao Shimamura

IPC: H04L27/00 ,  H04L1/00 ,  H04L27/18 ,  H04L27/20 ,  H04L27/227 ,  H04L1/10

CPC classification number: H04L1/0061 ,  H04L27/2046 ,  H04L27/2277

Abstract: A code error detection system in a digital phase modulation communication system comprises on the transmitter side a first code train generator for generating a pseudo-random code train and a second code train generator for generating codes which are complementary to each other at n-bit intervals. A 4-phase phase modulator is driven by another code representative of the exclusive OR function of the pseudo-random and complementary codes.

公开(公告)号：US3913067A

公开(公告)日：1975-10-14

申请号：US37014373

申请日：1973-06-14

Applicant: GOLDBERG LESLIE LOUIS

Inventor： GOLDBERG LESLIE LOUIS

IPC: G06K5/00 ,  G07F7/12 ,  G09C1/10 ,  H03K13/34 ,  G06F11/10 ,  G06K5/02 ,  H04L1/10

CPC classification number: G06K5/00 ,  G06Q20/04

Abstract: The specification discloses a check digit verification apparatus having the following novel concepts 1. THE USE OF A READ-ONLY STORE (16) TO HOLD TABLES OF REMAINDER VALUES WHEREBY TO OBVIATE THE NEED FOR MULTIPLICATION COMPUTING ABILITY; 2. THE USE OF REMAINDER VALUES APPROPRIATE TO THE RESPECTIVE DIGITS OF AN IDENTITY NUMBER TO BE VERIFIED, AND SUMMATION OF THOSE REMAINDER VALUES TO PROVIDE AN OVERALL REMAINDER VALUE FOR THE IDENTITY NUMBER; 3. THE USE OF A REMAINDER VALUE ACCUMULATING STORE (23) HAVING A NUMBER OF STAGES EQUAL TO THE MODULUS OF THE SYSTEM, SO THAT THE CONTENTS OF THE STORE IS AN ACCUMULATED REMAINDER VALUE, THUS OBVIATING THE NEED FOR A ''DIVISION'' COMPUTING ABILITY; AND 4. THE USE OF A REGISTER (55) FOR TEMPORARILY STORING THE DIGITS OF AN IDENTITY NUMBER WHICH IS TO BE VERIFIED, AND FOR RETAINING A PREDETERMINED INITIAL GROUP OF DIGITS AFTER ALL THE DIGITS OF THE IDENTITY NUMBER HAVE BEEN TRANSFERRED INTO THE VERIFICATION MEANS, WHEREBY TO REDUCE THE NUMBER OF DIGITS THAT HAVE TO BE KEYED-IN WHEN THE NEXT IDENTITY NUMBER FOR VERIFICATION INCLUDES THE RETAINED INITIAL GROUP OF DIGITS.

公开(公告)号：US3909783A

公开(公告)日：1975-09-30

申请号：US45830774

申请日：1974-04-05

Applicant: CASIO COMPUTER CO LTD

Inventor： KASHIO TOSHIO

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/004

Abstract: A coded information signal forming apparatus comprising a judgement circuit for judging whether the total number of bits of ''''1'''' or ''''0'''' constituting binary-coded unit of information defined by a division code is odd or even; and means for inverting to 1 the polarity of the least significant bit of a division code immediately following said unit of information in the case where said total bit number is odd, whereby a coded information signal suitable for checking the presence of bit errors in said unit of information can be detected.

Abstract translation: 一种编码信息信号形成装置，包括：判断电路，用于判断构成由分割码定义的信息的二进制编码单位的“1”或“0”的总数是奇数还是偶数; 以及用于在所述总位数为奇数的情况下将与紧接在所述信息单元之后的分割代码的最低有效位的极性反相为1的装置，由此编码信息信号适合于检查所述单元中的位错误的存在 的信息可以被检测。

公开(公告)号：US3872432A

公开(公告)日：1975-03-18

申请号：US45952274

申请日：1974-04-10

Applicant: ITT

Inventor： BISMARCK OTTO HERBERT

IPC: H03M13/33 ,  H04L1/00 ,  H04L7/02 ,  G06F11/12 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L7/0062 ,  H03M13/33 ,  H04L1/0054

Abstract: A Viterbi decoder sync circuit is disclosed that provides an optimum synchronization, that is, synchronized as to phase, proper sequence of binary 1''s and binary 0''s in selected output coded data relative to the received data stream, and as to sync, proper location in time of the selected output coded data relative to the received data stream so that bits 1, 2 and 3 of the selected output coded data word are time coincident with bits 1, 2 and 3 of the received coded data word. The sync circuit disclosed herein accomplishes this by determining the spread between the maximum path metrics and next-to-maximum path metrics and averaging the determined spread over a predetermined number of decoding cycles.

Abstract translation: 公开了一种维特比解码器同步电路，其提供最佳同步，即相对于所接收的数据流，在选定的输出编码数据中的二进制1和二进制0的相位适当序列同步，并且同步于时间上适当的位置 所选择的输出编码数据相对于所接收的数据流，使得所选择的输出编码数据字的位1,2和3与接收的编码数据字的位1,2和3一致。 本文公开的同步电路通过确定最大路径度量和下一至最大路径度量之间的扩展并在预定数量的解码周期上对确定的扩展进行平均来实现。

公开(公告)号：US3836957A

公开(公告)日：1974-09-17

申请号：US37370873

申请日：1973-06-26

Applicant: IBM

Inventor： DUKE K ,  MESSINA B

IPC: G06F12/16 ,  G06F11/08 ,  G06F11/10 ,  H04L1/10 ,  G06F11/12

CPC classification number: G06F11/1048

Abstract: Disclosed is a data transfer mechanism between the data bus of a data processing system and a data store. The data transfer mechanism includes common logic for converting between parity coded data on the data bus and error checking and correcting (ECC) coded data associated with the data store. Parity errors in data for presentation to the data store are detected, and single error correction and double error detection (SEC/DEC) syndrome bits are generated from the original ECC bits when data is to be read from the store and presented to the data bus. Additional circuitry is included to cause a signal indicating a single parity error on the data bus to modify the ECC bits generated for presentation to the data store with the data. On a subsequent read of the data from the data store, the modified ECC bits will produce a set of syndrome bits, specially recognized, to cause the data to be presented to the data bus with the original byte parity error recreated for subsequent detection.

Abstract translation: 公开了数据处理系统的数据总线与数据存储器之间的数据传送机制。 数据传输机制包括用于在数据总线上的奇偶校验编码数据之间进行转换的通用逻辑，以及与数据存储相关联的错误校验（ECC）编码数据。 检测用于呈现给数据存储器的数据中的奇偶校验错误，并且当从存储器读取数据并将其呈现给数据总线时，从原始ECC位产生单个错误校正和双重错误检测（SEC / DEC）校验位 。 包括额外的电路以引起指示数据总线上的单个奇偶校验错误的信号，以修改生成的用于使用数据呈现给数据存储器的ECC位。 在随后从数据存储器中读取数据时，修改后的ECC位将产生一组专门识别的校正子位，以使数据以原始字节奇偶校验错误的形式呈现给数据总线，用于后续检测。

公开(公告)号：US3831144A

公开(公告)日：1974-08-20

申请号：US36880373

申请日：1973-06-11

Applicant: MOTOROLA INC

Inventor： EN J

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/004

Abstract: An error detecting coding and decoding system employing an encoder having a plurality of shift register systems for generating independent sequences of check bits for multiple level checks. A decoder having similar shift registers is employed to regenerate the check bits from the transmitted information and to compare the locally generated check bits with the transmitted check bits generated by the encoder.

Abstract translation: 一种采用具有多个移位寄存器系统的编码器的错误检测编码和解码系统，用于产生用于多级检查的独立的校验位序列。 采用具有类似移位寄存器的解码器从所发送的信息中重新产生校验位，并将本地产生的校验位与由编码器产生的发送校验位进行比较。

公开(公告)号：US3825893A

公开(公告)日：1974-07-23

申请号：US36448073

申请日：1973-05-29

Applicant: IBM

Inventor： BOSSEN D ,  PATEL A ,  HONG S ,  HSIAO M

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19 ,  H04L1/10

CPC classification number: G06F11/1012 ,  H03M13/19

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1''s and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.