公开(公告)号：US3872432A

公开(公告)日：1975-03-18

申请号：US45952274

申请日：1974-04-10

Applicant: ITT

Inventor： BISMARCK OTTO HERBERT

IPC: H03M13/33 ,  H04L1/00 ,  H04L7/02 ,  G06F11/12 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L7/0062 ,  H03M13/33 ,  H04L1/0054

Abstract: A Viterbi decoder sync circuit is disclosed that provides an optimum synchronization, that is, synchronized as to phase, proper sequence of binary 1''s and binary 0''s in selected output coded data relative to the received data stream, and as to sync, proper location in time of the selected output coded data relative to the received data stream so that bits 1, 2 and 3 of the selected output coded data word are time coincident with bits 1, 2 and 3 of the received coded data word. The sync circuit disclosed herein accomplishes this by determining the spread between the maximum path metrics and next-to-maximum path metrics and averaging the determined spread over a predetermined number of decoding cycles.

Abstract translation: 公开了一种维特比解码器同步电路，其提供最佳同步，即相对于所接收的数据流，在选定的输出编码数据中的二进制1和二进制0的相位适当序列同步，并且同步于时间上适当的位置 所选择的输出编码数据相对于所接收的数据流，使得所选择的输出编码数据字的位1,2和3与接收的编码数据字的位1,2和3一致。 本文公开的同步电路通过确定最大路径度量和下一至最大路径度量之间的扩展并在预定数量的解码周期上对确定的扩展进行平均来实现。