公开(公告)号：US08422388B2

公开(公告)日：2013-04-16

申请号：US12767714

申请日：2010-04-26

Applicant: Thomas E. Katis ,  James T. Panttaja ,  Mary G. Panttaja ,  Matthew J. Ranney

Inventor： Thomas E. Katis ,  James T. Panttaja ,  Mary G. Panttaja ,  Matthew J. Ranney

IPC: H04J1/16 ,  H04J3/14 ,  H04L1/10 ,  H04L12/26

CPC classification number: G10L19/0019 ,  H04L51/04 ,  H04L51/066 ,  H04L51/26 ,  H04L65/1083 ,  H04L65/4015 ,  H04L65/4053 ,  H04L65/604

Abstract: A method for gracefully extending the range and/or capacity of voice communication systems is disclosed. The method involves the persistent storage of voice media on a communication device. When the usable bit rate on the network is poor and below that necessary for conducting a live conversation, voice media is transmitted and received by the communication device at the available usable bit rate on the network. Although latency may be introduced, the persistent storage of both transmitted and received media of a conversation provides the ability to extend the useful range of wireless networks beyond what is required for live conversations. In addition, the capacity and robustness in not being affected by external interferences for both wired and wireless communications is improved.

公开(公告)号：US08155004B2

公开(公告)日：2012-04-10

申请号：US11234135

申请日：2005-09-26

Applicant: Ji-hoon Lee ,  Jung-ho Kim

Inventor： Ji-hoon Lee ,  Jung-ho Kim

IPC: H04L12/28 ,  H04L1/10

CPC classification number: H04W40/28 ,  H04L45/122 ,  H04L45/20 ,  H04W40/30 ,  H04W84/18

Abstract: Disclosed is a mobile network system based on ad hoc on-demand distance vector (AODV) routing algorithm, including: a destination node: a source node for transmitting a data packet to the destination node by following a communication path; and a mobile node for receiving the data packet from a plurality of intermediate nodes located on the communication path, checking hop count numbers for the plurality of intermediate nodes, and establishing a communication path with a first node having a least number of hops and a second node having a most number of hops. Therefore, an optimum changeable communication path is searched in consideration of mobility of the mobile node. In result, communication speed is increased and the lifespan of the network is extended.

Abstract translation: 公开了一种基于自适应按需距离向量（AODV）路由算法的移动网络系统，包括：目的地节点：通过跟随通信路径将数据分组发送到目的地节点的源节点; 以及移动节点，用于从位于所述通信路径上的多个中间节点接收所述数据分组，检查所述多个中间节点的跳数计数，以及建立与具有最少跳数的第一节点和第二节点的通信路径 节点具有最多的跳数。 因此，考虑到移动节点的移动性，搜索最佳可变通信路径。 结果，通信速度提高，网络的寿命延长。

公开(公告)号：US07782766B2

公开(公告)日：2010-08-24

申请号：US10942043

申请日：2004-09-16

Applicant: Takahiro Ohkuma ,  Daisuke Kawasaki ,  Kazuhiko Isoyama

Inventor： Takahiro Ohkuma ,  Daisuke Kawasaki ,  Kazuhiko Isoyama

IPC: H04L1/10

CPC classification number: H04Q9/00

Abstract: The present invention relates to a data collection system and a data collection method in a sensor network, enabling sensor modules to consume lower amounts of power. The base station transmits data collection request signals to one or more sensor modules which are lower than the base station by 1 in a tree structure. Each sensor module which has received the data collection request signal transfers the signal to one or more sensor modules which are lower than the module by 1. The base station regards the transfer of the signal as ACK for the data collection request signal transmitted therefrom to the sensor module which is lower than the base station by 1. The transmission of a data collection acknowledgement signal starts from a sensor module at the low-order end. When a sensor module receives the data collection acknowledgement signal from a downstream sensor module which is lower than the module by 1, the module transmits the signal to an upstream sensor module which is higher than the module by 1. The downstream sensor module regards the transmission of the signal as ACK for the data collection acknowledgement signal transmitted therefrom, and enters standby mode. In this manner, the sensor modules enter standby mode in sequence starting from the sensor module at the low-order end. Thereby, it is possible to achieve reductions in the frequency of signal transmission while maintaining reliable data communication. Thus, each module consumes lower amounts of power.

Abstract translation: 本发明涉及传感器网络中的数据收集系统和数据收集方法，使得传感器模块能够消耗更少的功率。 基站以树结构将数据收集请求信号发送到低于基站1的一个或多个传感器模块。 已经接收到数据收集请求信号的每个传感器模块将信号传送到低于模块1的一个或多个传感器模块。基站将信号的传送视为从其发送的数据收集请求信号的ACK 传感器模块比基站低1。数据采集确认信号的传输从低端的传感器模块开始。 当传感器模块从低于模块1的下游传感器模块接收到数据收集确认信号时，模块将信号发送到高于模块1的上游传感器模块。下游传感器模块将传输 的信号作为从其发送的数据收集确认信号的ACK，并进入待机模式。 以这种方式，传感器模块按顺序从低端的传感器模块进入待机模式。 由此，可以在保持可靠的数据通信的同时实现信号发送的频率的降低。 因此，每个模块消耗较少的功率。

公开(公告)号：US07653160B2

公开(公告)日：2010-01-26

申请号：US11266359

申请日：2005-11-04

Applicant: Olli Piirainen

Inventor： Olli Piirainen

IPC: H04L1/00 ,  H04L1/02 ,  H04L1/10 ,  H04L7/02 ,  H04J11/00

CPC classification number: H04B1/1027 ,  H04B17/373

Abstract: The invention relates to a method of estimating a noise and interference covariance matrix and to a receiver. The method comprises: estimating an initial noise and interference covariance matrix on the basis of a received signal; reducing the impact of the background noise of the receiver from the initial noise and interference covariance matrix for obtaining a residual matrix; accepting the obtained residual matrix when the residual matrix is at least approximately positive semidefinite; modifying the obtained residual matrix such that the positive semidefinity of the residual matrix is achieved when the residual matrix is not at least approximately positive semidefinite; and adding the impact of background noise back to the residual matrix for estimating a final noise and interference covariance matrix.

Abstract translation: 本发明涉及一种估计噪声和干扰协方差矩阵和接收机的方法。 该方法包括：基于接收信号估计初始噪声和干扰协方差矩阵; 从初始噪声和干扰协方差矩阵减小接收机的背景噪声对获得残余矩阵的影响; 当残余矩阵至少约为正半定数时，接受所获得的残余矩阵; 修改所获得的残余矩阵，使得当残余矩阵不至少近似为正半固定时，实现残余矩阵的正半精度; 并将背景噪声的影响加回到残差矩阵中，以估计最终的噪声和干扰协方差矩阵。

公开(公告)号：US4191970A

公开(公告)日：1980-03-04

申请号：US906115

申请日：1978-05-15

Applicant: Hans S. Witsenhausen ,  Aaron D. Wyner

Inventor： Hans S. Witsenhausen ,  Aaron D. Wyner

IPC: G06T9/00 ,  H04N7/32 ,  H04N7/66 ,  H04N19/895 ,  H04N5/21 ,  H04L1/10 ,  H04N7/04 ,  H04N7/12

CPC classification number: H04N19/895 ,  H04N19/152 ,  H04N19/50

Abstract: Error-correcting code theory is utilized in a video signal interframe coding system which requires no transmitter frame memory. In the transmitter, each of a plurality of n-bit words representing respective portions of the current frame is transformed into the corresponding k-bit syndrome of a selected (n,k) error-correcting code. As the syndrome of each word is received at the receiver, the corresponding word from the previous frame is read out of a receiver frame memory and its syndrome is formed. The received and formed syndromes are subtracted from one another and passed through an error-correcting code decoder. The previous-frame word is added to the decoder output, yielding the current-frame n-bit word.

Abstract translation: 在不需要发送机帧存储器的视频信号帧间编码系统中使用纠错码理论。 在发送器中，表示当前帧的各个部分的多个n位字中的每一个被变换成所选择的（n，k）纠错码的相应的k位校正子。 由于在接收机处接收到每个字的校正子，所以从接收机帧存储器中读出来自前一帧的相应字，并形成其综合征。 接收和形成的综合征彼此相减并通过纠错码解码器。 将前一帧字添加到解码器输出，产生当前帧n位字。

公开(公告)号：US4092630A

公开(公告)日：1978-05-30

申请号：US732995

申请日：1976-10-15

Applicant: Hendrik Cornelis Anthony VAN Duuren ,  Herman DA Silva

Inventor： Hendrik Cornelis Anthony VAN Duuren ,  Herman DA Silva

IPC: H04L1/16 ,  G06F11/00 ,  G08C20060101 ,  G08C25/00 ,  H04B1/00 ,  H04L1/18 ,  H04L7/00 ,  H04L1/10

Abstract: A system for reducing the time for repeating erroneous signals through a series of interconnected ARQ-circuits (automatic error correction circuits), in which the durations of the repetition cycles of the ARQ-circuits, as compared to one another, are not equal. The system comprises means at a connection point and capable of storing a number of signals related to each propagation time of a circuit located before the connection point, when a circuit located behind the connection point goes through a repetition procedure including means for generating a special signal to indicate when a repetition procedure is in process in one of said ARQ interconnected circuits to prevent the other interconnected ARQ circuits from also going through their repetition procedures.

公开(公告)号：US3944973A

公开(公告)日：1976-03-16

申请号：US538937

申请日：1975-01-06

Applicant: Jean-Jacques Masson

Inventor： Jean-Jacques Masson

IPC: H03M13/19 ,  H04L1/10 ,  G06F11/10

CPC classification number: H03M13/19

Abstract: In information handling systems, syndrome and correction codes adapted for error signalling and correcting operations are obtained by processing words each made of a definite number of bytes, each byte having a same number of bits and one of the bytes being comprised of the parity incoming bits of the other bytes. An error syndrome and correction code forming device is described which comprises first and second stages of modulo-2 adders (i.e. exclusive-OR circuits), the number of adders in the second stage being equal to the number of bits in the required code, wherein the adders of the first stage form the parity check bits of the bytes and further bits from selective combinations of bits in the word and wherein the bits outputting the adders of the first stage are distributed, together with further bits of the word, to the inputs of the adders of the second stage. Substantially all the adders of the first stage have at least as many inputs as there are information bytes in the word to be processed and substantially all the outputs of said first stage adders are applied to inputs of at least two adders of the second stage.

Abstract translation: 在信息处理系统中，通过处理由确定数量的字节组成的每个字节，每个字节具有相同数量的位并且一个字节由奇偶校验输入位组成，从而获得适用于错误信号和校正操作的校正和校正码 的其他字节。 描述了包括模2加法器的第一和第二级（即异或电路）的错误综合征和校正码形成装置，第二级中的加法器数量等于所需代码中的位数，其中 第一级的加法器形成字节的奇偶校验位和从字中的位的选择性组合的其他位，并且其中输出第一级的加法器的位与该字的另外位一起分配给输入 的第二阶段的加法器。 基本上第一级的所有加法器至少具有与要处理的字中的信息字节一样多的输入，并且所述第一级加法器的基本上所有的输出被应用于第二级的至少两个加法器的输入。

公开(公告)号：US3940736A

公开(公告)日：1976-02-24

申请号：US491306

申请日：1974-07-24

Applicant: Hiroshi Inaba ,  Etsugo Yoneda

Inventor： Hiroshi Inaba ,  Etsugo Yoneda

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/0061

Abstract: A system for monitoring the transmission of a digital code is disclosed wherein a block consisting of a predetermined number of bits is extracted at a predetermined cycle from an information pulse train before the bit rate conversion thereof so that a check code corresponding to the states of this block may be formed, and inserted into the time slots formed by the bit rate conversion of the information pulse train, and the check code with the information pulse train after bit rate conversion, is transmitted to a receiving equipment. In the receiving equipment, a check code is formed from the received information pulse train, whose bit rate is restored to its original rate, in a manner exactly similar to that used in the transmitting equipment and is compared with the transmitted check code, that is, the check code is extracted from the received pulse train. Therefore, the whole transmission system including the channel before a bit rate converter in the transmitting equipment and the channel after a bit rate converter in the receiving equipment may be monitored.

Abstract translation: 公开了一种用于监视数字码的传输的系统，其中由比特率转换之前的信息脉冲串以预定的周期从预定的周期提取由预定数量的比特组成的块，使得对应于该状态的校验码 可以形成块，并将其插入由信息脉冲串的比特率转换形成的时隙中，并且将比特率转换后的信息脉冲串的校验码发送到接收设备。 在接收设备中，以接收到的信息脉冲串形成校验码，该信号脉冲序列的比特率恢复到其原始速率，与发送设备中使用的信息脉冲序列完全相同，并与发送的校验码进行比较，即 从接收到的脉冲串中提取校验码。 因此，可以监视包括发送设备中的比特率转换器之前的信道和接收设备中的比特率转换器之后的信道的整个传输系统。

公开(公告)号：US3906445A

公开(公告)日：1975-09-16

申请号：US51632574

申请日：1974-10-21

Applicant: MOTOROLA INC

Inventor： BECKMANN ROBERT M ,  LAMB JAMES A ,  NIEGLOS DONALD J ,  REYNOLDS GARY R

IPC: G06F13/00 ,  H04B7/26 ,  H04L1/00 ,  H04L29/12 ,  H04M11/00 ,  H04L1/10 ,  H04L1/06 ,  H04L1/08

CPC classification number: H04L1/00

Abstract: An alphanumeric terminal providing a digital message having a fixed portion consisting of the address of the receiver in sixteen bits, followed by a repeat of the address in sixteen bits, a status indication in four bits, a request in four bits and an acknowledge plus an indication of whether text follows in two bits; and a variable portion consisting of a text message of zero to 384 bits, which fixed and variable portions of the message have parity bits inserted after each digital word and are delayed and interleaved (every other bit) with a similar undelayed message to form a composite message, which composite message is preceded by a pseudo random code of 127 bits. The terminal also includes noise and error detection circuitry, associated with the receiver, which separates the two interleaved messages and compares them for similarity, checks the parity bits for correctness and compares the amplitude of each bit to a predetermined upper and lower level to determine whether the bit is noise or a portion of the signal. From the various noise and error checks the terminal then provides a decision as to whether a digital word is good or bad and, if the digital word is in error and comes within the text portion of the message, an asterisk appears in the visual display so that the operator can mentally determine what the character should be.

Abstract translation: 一个字母数字终端提供数字消息，该数字消息具有由十六位中的接收者的地址组成的固定部分，随后以16比特重复地址，4比特的状态指示，4比特的请求和确认加上 文本是否以两位表示; 以及由零到384位的文本消息组成的可变部分，该消息的固定和可变部分在每个数字字之后插入奇偶校验位，并且以类似的未延迟消息被延迟和交织（每隔一个位）形成复合 消息，哪个复合消息之前是127位的伪随机码。 终端还包括与接收机相关联的噪声和错误检测电路，其分离两个交错消息并将它们进行比较，以便进行相似性，检查奇偶校验位的正确性，并将每个位的幅度与预定的上限和下限进行比较，以确定是否 该位是噪声或信号的一部分。 从各种噪声和错误检查，终端然后提供关于数字字是好是坏的决定，如果数字字错误并且在消息的文本部分内，则在视觉显示中出现星号， 操作者可以精神上确定角色应该是什么。

公开(公告)号：US3893070A

公开(公告)日：1975-07-01

申请号：US43153074

申请日：1974-01-07

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  CORDI VINCENT A ,  HSIAO MU-YUE ,  SHIFFRIN BARRY N ,  GLICK ELLIS W

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10

CPC classification number: G06F11/1048

Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.

Abstract translation: 纠错和检测电路包括一个模块化编码器，其提供用于编码特定数量的数据位的最小数量的校验位。 提供了用于组合几个单元以在要编码较大数据字时产生最小数量的码位的装置。 还公开了一种使用该纠错电路的存储层级系统。