公开(公告)号：US3836957A

公开(公告)日：1974-09-17

申请号：US37370873

申请日：1973-06-26

Applicant: IBM

Inventor： DUKE K ,  MESSINA B

IPC: G06F12/16 ,  G06F11/08 ,  G06F11/10 ,  H04L1/10 ,  G06F11/12

CPC classification number: G06F11/1048

Abstract: Disclosed is a data transfer mechanism between the data bus of a data processing system and a data store. The data transfer mechanism includes common logic for converting between parity coded data on the data bus and error checking and correcting (ECC) coded data associated with the data store. Parity errors in data for presentation to the data store are detected, and single error correction and double error detection (SEC/DEC) syndrome bits are generated from the original ECC bits when data is to be read from the store and presented to the data bus. Additional circuitry is included to cause a signal indicating a single parity error on the data bus to modify the ECC bits generated for presentation to the data store with the data. On a subsequent read of the data from the data store, the modified ECC bits will produce a set of syndrome bits, specially recognized, to cause the data to be presented to the data bus with the original byte parity error recreated for subsequent detection.

Abstract translation: 公开了数据处理系统的数据总线与数据存储器之间的数据传送机制。 数据传输机制包括用于在数据总线上的奇偶校验编码数据之间进行转换的通用逻辑，以及与数据存储相关联的错误校验（ECC）编码数据。 检测用于呈现给数据存储器的数据中的奇偶校验错误，并且当从存储器读取数据并将其呈现给数据总线时，从原始ECC位产生单个错误校正和双重错误检测（SEC / DEC）校验位 。 包括额外的电路以引起指示数据总线上的单个奇偶校验错误的信号，以修改生成的用于使用数据呈现给数据存储器的ECC位。 在随后从数据存储器中读取数据时，修改后的ECC位将产生一组专门识别的校正子位，以使数据以原始字节奇偶校验错误的形式呈现给数据总线，用于后续检测。