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公开(公告)号：US3745525A
公开(公告)日：1973-07-10
申请号：US3745525D
申请日：1971-12-15
Applicant: IBM
CPC classification number: H03M13/19
Abstract: An error correcting system is provided for information sequences divided into bytes of b bits each. The information is encoded in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the sequence of message bytes. Each of the submatrices are concatenated iteratively by b so that the submatrices can be designated by Hr,b; H(r b),b; H(r 2b),b . . . H(2b c),b where r kb+c and 0
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公开(公告)号：US3851306A
公开(公告)日：1974-11-26
申请号：US30938872
申请日：1972-11-24
Applicant: IBM
Inventor： PATEL A
CPC classification number: G11B20/1833 , G11B20/18
Abstract: A method for correcting errors in up to three tracks or channels in a multi-track data system is provided. Message data is formed into a codeword by adding three check bytes thereto which are dependent on each other and are generated from the information bytes. After the data has undergone some form of transposition, at which time it is desirable to check for errors and correct any errors within the capability of the code, the transposed data is decoded so as to generate three syndromes. At the time of data transposition, error pointers may be provided. When the provided pointers indicate that either two or three tracks contain errors, error patterns are generated and added to the information already within the tracks in error, to correct the errors. If only one pointer is provided, a check is made to see whether or not another track is in error even though a pointer was not provided, and, if an additional track is in error, its pointer is generated. Thereafter these two tracks are corrected. Similarly, if no pointer is provided, a check is made to determine whether or not there was at least one track in error. If so, the pointer is generated and the error is corrected. An uncorrectable error indication is provided when errors are encountered that lie outside of the correction capability of the code.
Abstract translation: 提供了一种用于在多轨道数据系统中校正多达三个轨道或信道中的错误的方法。 消息数据通过将三个校验字节相加并形成为码字，并从信息字节生成。 在数据经历某种形式的转置之后，期望检查错误并纠正代码能力内的任何错误，转置的数据被解码以产生三个综合征。 在数据转置时，可能会提供错误指针。 当提供的指针指示两个或三个轨道包含错误时，错误模式被生成并被添加到已经在轨道内的信息中，以纠正错误。 如果仅提供一个指针，则即使没有提供指针，也检查另一个轨道是否有错误，并且如果附加轨道出错，则生成其指针。 此后，这两个轨道被校正。 类似地，如果没有提供指针，则进行检查以确定是否存在至少一个错误的轨道。 如果是，则生成指针并纠正错误。 当遇到不在代码的校正能力之外的错误时，提供不可校正的错误指示。
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公开(公告)号：US3786439A
公开(公告)日：1974-01-15
申请号：US3786439D
申请日：1972-12-26
Applicant: IBM
Inventor： MC DONALD E , PATEL A
CPC classification number: G11B20/1833
Abstract: Error detection is enhanced by using multiple independent error codes combined with nonlinear changes in the data field as applied to different error codes. Such nonlinear permutations increase the probability of detecting errors thereby maximizing the utilization of check bit redundancies. In a magnetic tape subsystem, error detection and correction can be enhanced by scrambling track-to-error code relationships between a plurality of independent codes. Tracks with the highest probability of errors, i.e., the outside tracks on a 1/2 inch tape, for example, are connected to nonadjacent inputs of error correction code apparatus. Additionally, the input-to-track relationship of various code apparatus can be scrambled, either permanently or during a tape transducing operation. The above permutations provide best advantage with selected error correction codes and systems having identifiable probability of error patterns.
Abstract translation: 通过使用多个独立的错误代码结合应用于不同错误代码的数据字段中的非线性变化来增强错误检测。 这种非线性置换增加了检测错误的可能性，从而最大化了校验位冗余的利用率。 在磁带子系统中，可以通过对多个独立代码之间的跟踪到错误代码关系进行加扰来增强错误检测和校正。 具有最高错误概率的轨道，例如1/2英寸磁带上的外部磁道，连接到纠错码装置的不相邻的输入端。 此外，可以永久地或在磁带传输操作期间扰乱各种代码设备的输入到轨道的关系。 上述排列为选择的纠错码和具有可识别的错误模式概率的系统提供了最佳的优点。
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Patent Agency Ranking
公开(公告)号：US3745528A
公开(公告)日：1973-07-10
申请号：US3745528D
申请日：1971-12-27
Applicant: IBM
Inventor： PATEL A
CPC classification number: G11B20/1833
Abstract: A system for correcting two tracks in error in a multi-track data arrangement is provided. The message data Z1, Z2, . . . Zk is encoded by adding two check bytes C1 and C2 thereto which are generated from the message data which is arranged in blocks of k bytes, where each byte has f bits of data arranged in a cross track direction, where f b X m and m and b are integers >1 and k is an integer 2
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公开(公告)号：US3714629A
公开(公告)日：1973-01-30
申请号：US3714629D
申请日：1971-06-01
Applicant: IBM
CPC classification number: H03M13/15
Abstract: A cyclic code is encoded for double error correction in accordance with the following parity check matrix: WHERE THE CODE LENGTH N IS GIVEN BY 2M-1 AND Alpha IS A PRIMITIVE ELEMENT OF GF(2m) represented by a binary column vector. Decoding of the coded message requires establishing a one to one correspondence between n2+n/2 distinct error patterns and the corresponding syndromes. The n2+n/2 distinct syndromes are mapped into n+1/2 fixed syndromes by an arithmetic operation as follows: The syndrome is obtained in two parts for an error in each of digit positions i and j given by: This syndrome is mapped into: There are only n+1/2 distinct values of S'' to cover all possible single and double errors. The error positions resulting from the corresponding S'' are then mapped into actual error locations i and j.
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公开(公告)号：US3745526A
公开(公告)日：1973-07-10
申请号：US3745526D
申请日：1971-12-20
Applicant: IBM
Abstract: An error correcting system is provided for a parallel track or parallel channel information handling system in which the information is divided into blocks of bytes of b-bits each. The information is encoded by attaching a plurality of check bytes in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the message bytes. Each of the submatrices are concatenated iteratively by b so that the matrix H can be designated by submatrices Hr,b; H(r b) , b; H(r 2b) ,b. . . H(2b c) ,b where r kb c and 0
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公开(公告)号：US3825893A
公开(公告)日：1974-07-23
申请号：US36448073
申请日：1973-05-29
Applicant: IBM
CPC classification number: G06F11/1012 , H03M13/19
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1''s and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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8.发明授权Data coding with stable base line for recording and transmitting binary data 失效使用稳定的基线进行数据编码，用于记录和传输二进制数据
公开(公告)号：US3810111A
公开(公告)日：1974-05-07
申请号：US31798072
申请日：1972-12-26
Applicant: IBM
Inventor： PATEL A
IPC: H03M5/14 , G06K7/00 , G11B20/14 , H03M7/00 , H03M7/14 , H04L25/48 , H04L25/49 , H03K13/00 , G06F5/00 , H04L3/00
CPC classification number: H04L25/4906 , G11B20/1426
Abstract: An improved method and apparatus for encoding and decoding binary data is disclosed. For improving data density for storage or transmission, the waveform has an upper frequency limit such that transitions in the encoded waveform occur no closer together than the time for one data digit. To provide suitable clocking for waveform detection circuits, the waveform has a lower frequency limit that transitions occur no farther apart than two data digit times. In addition, the waveform is symetrical about a zero signal level within narrow limits. The encoding is called ''''zero modulation'''' (or ZM) for zero direct component. Since the waveform has a constrained direct component, it can be used with circuit devices of the type that will not transmit a direct component. Circuits for detecting errors in the decoded waveform are also disclosed.
Abstract translation: 公开了一种用于对二进制数据进行编码和解码的改进方法和装置。 为了提高存储或传输的数据密度，波形具有较高的频率限制，使得编码波形中的转换与一个数据位的时间不在一起。 为了为波形检测电路提供合适的时钟，波形具有较低的频率限制，转换发生的距离不会超过两个数字数字时间。 此外，波形是在窄范围内关于零信号电平的对称。 对于零直接分量，编码称为“零调制”（或ZM）。 由于波形具有受限制的直接分量，因此可以与不传输直接分量的电路设备一起使用。 还公开了用于检测解码波形中的错误的电路。
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