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Patent Agency Ranking
公开(公告)号：US3764788A
公开(公告)日：1973-10-09
申请号：US3764788D
申请日：1972-06-30
Applicant: IBM
IPC: G06F11/22 , G01R31/3183 , G06F11/16 , H03K19/003 , G06F11/00
CPC classification number: H03K19/003 , G01R31/318342
Abstract: A new circuit is provided for checking for errors caused by most but not all of the faults that might occur in a network of logic gates. One part of the checking circuits, called a ''''1 cover'''' produces an output that is designated C1, and includes selected prime implicants of the function, F, of the newtork being checked. Thus, if there is no fault in either the circuit being checked or in the 1 cover circuit, C1 1 implies that F 1. A comparison circuit is provided to produce an error signifying output, E, for the condition C1 1 and F 0. Similarly, another part of the checking circuit, called a ''''0 cover'''' produces an output that is designated CO and includes selected prime implicants of the complement, F, of the circuit being checked. The comparison part of the checking circuit detects the condition CO 1, F 0, as an error condition. Thus, the checking circuit of this invention operates according to the equation E FCO + FC1. The circuit responds to a high portion of the possible faults in the circuit being checked but it has many fewer components than the circuit being checked.
Abstract translation: 提供了一种新电路，用于检查由逻辑门网络中可能发生的大多数但不是全部故障引起的错误。 检查电路的一部分称为“1盖”，产生一个被指定为C1的输出，并且包括被检查的纽索的函数F的选定的主要含义。 因此，如果在被检查的电路中或在1盖电路中没有故障，则C1 = 1意味着F = 1。提供比较电路以产生对于条件C1 = 1的错误表示输出E， F = 0。
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公开(公告)号：US3745525A
公开(公告)日：1973-07-10
申请号：US3745525D
申请日：1971-12-15
Applicant: IBM
CPC classification number: H03M13/19
Abstract: An error correcting system is provided for information sequences divided into bytes of b bits each. The information is encoded in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the sequence of message bytes. Each of the submatrices are concatenated iteratively by b so that the submatrices can be designated by Hr,b; H(r b),b; H(r 2b),b . . . H(2b c),b where r kb+c and 0
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公开(公告)号：US3714629A
公开(公告)日：1973-01-30
申请号：US3714629D
申请日：1971-06-01
Applicant: IBM
CPC classification number: H03M13/15
Abstract: A cyclic code is encoded for double error correction in accordance with the following parity check matrix: WHERE THE CODE LENGTH N IS GIVEN BY 2M-1 AND Alpha IS A PRIMITIVE ELEMENT OF GF(2m) represented by a binary column vector. Decoding of the coded message requires establishing a one to one correspondence between n2+n/2 distinct error patterns and the corresponding syndromes. The n2+n/2 distinct syndromes are mapped into n+1/2 fixed syndromes by an arithmetic operation as follows: The syndrome is obtained in two parts for an error in each of digit positions i and j given by: This syndrome is mapped into: There are only n+1/2 distinct values of S'' to cover all possible single and double errors. The error positions resulting from the corresponding S'' are then mapped into actual error locations i and j.
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公开(公告)号：US3745526A
公开(公告)日：1973-07-10
申请号：US3745526D
申请日：1971-12-20
Applicant: IBM
Abstract: An error correcting system is provided for a parallel track or parallel channel information handling system in which the information is divided into blocks of bytes of b-bits each. The information is encoded by attaching a plurality of check bytes in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the message bytes. Each of the submatrices are concatenated iteratively by b so that the matrix H can be designated by submatrices Hr,b; H(r b) , b; H(r 2b) ,b. . . H(2b c) ,b where r kb c and 0
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公开(公告)号：US3825893A
公开(公告)日：1974-07-23
申请号：US36448073
申请日：1973-05-29
Applicant: IBM
CPC classification number: G06F11/1012 , H03M13/19
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1''s and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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