公开(公告)号：US3764788A

公开(公告)日：1973-10-09

申请号：US3764788D

申请日：1972-06-30

Applicant: IBM

Inventor： HONG S ,  JONES D ,  OSTAPKO D

IPC: G06F11/22 ,  G01R31/3183 ,  G06F11/16 ,  H03K19/003 ,  G06F11/00

CPC classification number: H03K19/003 ,  G01R31/318342

Abstract: A new circuit is provided for checking for errors caused by most but not all of the faults that might occur in a network of logic gates. One part of the checking circuits, called a ''''1 cover'''' produces an output that is designated C1, and includes selected prime implicants of the function, F, of the newtork being checked. Thus, if there is no fault in either the circuit being checked or in the 1 cover circuit, C1 1 implies that F 1. A comparison circuit is provided to produce an error signifying output, E, for the condition C1 1 and F 0. Similarly, another part of the checking circuit, called a ''''0 cover'''' produces an output that is designated CO and includes selected prime implicants of the complement, F, of the circuit being checked. The comparison part of the checking circuit detects the condition CO 1, F 0, as an error condition. Thus, the checking circuit of this invention operates according to the equation E FCO + FC1. The circuit responds to a high portion of the possible faults in the circuit being checked but it has many fewer components than the circuit being checked.

Abstract translation: 提供了一种新电路，用于检查由逻辑门网络中可能发生的大多数但不是全部故障引起的错误。 检查电路的一部分称为“1盖”，产生一个被指定为C1的输出，并且包括被检查的纽索的函数F的选定的主要含义。 因此，如果在被检查的电路中或在1盖电路中没有故障，则C1 = 1意味着F = 1。提供比较电路以产生对于条件C1 = 1的错误表示输出E， F = 0。