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    Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation
    21.
    发明授权
    Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation 有权

    公开(公告)号：US10110239B1

    公开(公告)日：2018-10-23

    申请号：US15940681

    申请日：2018-03-29

    申请人： Oracle International Corporation

    发明人： Guanghua Shu ,  Frankie Y. Liu ,  Suwen Yang ,  Ziad Saleh Shehadeh ,  Eric Y. Chang

    IPC分类号： H04L7/00 ,  H03L7/099 ,  H03K5/156 ,  H03L7/24 ,  H03K3/03 ,  H03L7/087

    摘要： During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator. Finally, the system uses a gating mechanism to periodically suppress the injected pulses produced by the injection pulse generator to enable the frequency-tracking path to detect and remediate frequency errors without interference from phase adjustments.

    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR
    24.
    发明申请
    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR 审中-公开

    公开(公告)号：US20180013438A1

    公开(公告)日：2018-01-11

    申请号：US15632063

    申请日：2017-06-23

    申请人： Rambus Inc.

    发明人： Jared L. Zerbe ,  Masum Hossain

    IPC分类号： H03L7/24 ,  H03L1/00 ,  H03K3/03 ,  H03L7/06

    CPC分类号： H03L7/24 ,  H03K3/0307 ,  H03K3/0315 ,  H03L1/00 ,  H03L7/06

    摘要： Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more

    Multi-scope control and synchronization system
    29.
    发明授权
    Multi-scope control and synchronization system 有权

    公开(公告)号：US09651579B2

    公开(公告)日：2017-05-16

    申请号：US14724302

    申请日：2015-05-28

    申请人： Tektronix, Inc.

    发明人： Barton T. Hickman ,  Jed H. Andrews ,  Jeffrey W. Mucha

    IPC分类号： H04L7/00 ,  G01R13/32 ,  H03L7/24 ,  G01R13/02

    CPC分类号： G01R13/32 ,  G01R13/0254 ,  H03L7/24

    摘要： A test and measurement system for synchronizing multiple oscilloscopes including a host oscilloscope and at least one client oscilloscope. The host oscilloscope includes a host timebase clock configured to output a clock signal, a host digitizer including a digitizer synchronization clock based on the clock signal, and a host acquisition controller includes a trigger synchronization clock based the clock signal and outputs a run signal to begin an acquisition of an input signal. Each client oscilloscope includes a client timebase clock configured to receive the clock signal from the host timebase clock and output the clock signal, a client digitizer including a digitizer synchronization clock based on the clock signal, and a client acquisition controller includes a trigger synchronization clock based on the clock signal and receives the run signal from the host acquisition controller and begins an acquisition of another input signal based on the run signal.

    Digital fractional-N multiplying injection locked oscillator
    30.
    发明授权
    Digital fractional-N multiplying injection locked oscillator 有权

    公开(公告)号：US09614537B1

    公开(公告)日：2017-04-04

    申请号：US15093655

    申请日：2016-04-07

    申请人： Xilinx, Inc.

    发明人： Romesh Kumar Nandwana ,  Parag Upadhyaya

    IPC分类号： H03L7/06 ,  H03L7/197 ,  H03L7/24 ,  H03L7/099

    CPC分类号： H03L7/24 ,  H03L7/0805 ,  H03L7/081 ,  H03L2207/06 ,  H03L2207/50

    摘要： An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.