公开(公告)号：US09614537B1

公开(公告)日：2017-04-04

申请号：US15093655

申请日：2016-04-07

申请人： Xilinx, Inc.

发明人： Romesh Kumar Nandwana ,  Parag Upadhyaya

IPC分类号： H03L7/06 ,  H03L7/197 ,  H03L7/24 ,  H03L7/099

CPC分类号： H03L7/24 ,  H03L7/0805 ,  H03L7/081 ,  H03L2207/06 ,  H03L2207/50

摘要： An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.