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1328 条记录 (耗时 0.026 秒)

    POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS
    21.
    发明申请
    POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS 有权
    集成电路电源管理系统

    公开(公告)号：US20160134289A1

    公开(公告)日：2016-05-12

    申请号：US14539697

    申请日：2014-11-12

    申请人： Xilinx, Inc.

    发明人： Austin H. Lesea

    IPC分类号： H03K19/177 ,  H03K19/0175

    CPC分类号： H03K19/17772 ,  H03K19/00384 ,  H03K19/017509 ,  H03K19/17784

    摘要： An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

    摘要翻译： 一种装置包括多个可编程硬件资源和设置在IC芯片上的模数转换器（ADC）。 ADC被配置为量化IC芯片的一个或多个模拟参数的值。 该装置还包括配置控制电路，配置为响应于一组配置数据对可编程硬件资源进行编程。 可编程硬件资源被编程为实现由配置数据指定的一组电路，并将ADC连接到IC芯片的相应节点，以对模拟参数进行采样。 该装置还包括耦合到ADC并被配置为基于来自ADC的一个或多个模拟参数的量化值产生控制信号的接口电路。 接口电路将控制信号输出到耦合到IC芯片的电源端子的电源。

    OUTPUT DRIVER CIRCUIT WITH AUTO-EQUALIZATION BASED ON DRIVE STRENGTH CALIBRATION
    22.
    发明申请
    OUTPUT DRIVER CIRCUIT WITH AUTO-EQUALIZATION BASED ON DRIVE STRENGTH CALIBRATION 有权
    基于驱动强度校准的自动均衡的输出驱动电路

    公开(公告)号：US20160094202A1

    公开(公告)日：2016-03-31

    申请号：US14503090

    申请日：2014-09-30

    申请人： QUALCOMM Incorporated

    发明人： Timothy Mowry Hollis ,  Thomas Clark Bryan ,  Mark Wayland

    IPC分类号： H03K3/011 ,  G11C11/4096

    CPC分类号： H03K3/011 ,  G11C11/4096 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018585

    摘要： Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

    摘要翻译： 公开了基于来自校准驱动电路的输出阻抗的信息来均衡输出驱动器电路的系统和方法。 由校准产生的设置称为校准代码。 输出驱动器电路包括多个上拉元件，其在输出为高电平时使能或禁止产生期望的输出阻抗，并且当输出为低电平时启用或禁用以产生所需输出阻抗的多个下拉元件。 启用的上拉元件数量和启用的下拉元件数量通过校准设置。 校准的结果（即，上拉的使能元件数量和下拉使能元件的数量）用于设置预加重量的控制和/或设置控制输出 压摆率。

    SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE
    23.
    发明申请
    SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE 审中-公开
    半导体器件，显示模块和电子器件

    公开(公告)号：US20160090291A1

    公开(公告)日：2016-03-31

    申请号：US14859681

    申请日：2015-09-21

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Atsushi UMEZAKI

    IPC分类号： B81B3/00 ,  B81B7/00 ,  H01L27/12

    CPC分类号： B81B3/0083 ,  B81B7/008 ,  G09G3/3466 ,  G09G2300/08 ,  G09G2310/0262 ,  H01L27/1225 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/00384 ,  H03K19/018521

    摘要： An object is to continuously apply voltage to a MEMS device using first to fifth or sixth transistors. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor. A gate of the second transistor is electrically connected to the one of the source and the drain of the third transistor. A gate of the fourth transistor is electrically connected to the gate of the first transistor. The MEMS device is electrically connected to the one of the source and the drain of the first transistor.

    摘要翻译： 目的是使用第一至第五或第六晶体管将电压连续地施加到MEMS器件。 第一晶体管的源极和漏极之一电连接到第二晶体管的源极和漏极之一。 第三晶体管的源极和漏极之一电连接到第四晶体管的源极和漏极之一。 第一晶体管的栅极电连接到第五晶体管的源极和漏极之一。 第二晶体管的栅极电连接到第三晶体管的源极和漏极之一。 第四晶体管的栅极电连接到第一晶体管的栅极。 MEMS器件电连接到第一晶体管的源极和漏极之一。

    Circuit and Method for Detection and Compensation of Transistor Mismatch
    24.
    发明申请
    Circuit and Method for Detection and Compensation of Transistor Mismatch 有权
    晶体管不匹配的检测和补偿电路及方法

    公开(公告)号：US20160013792A1

    公开(公告)日：2016-01-14

    申请号：US14772834

    申请日：2014-03-05

    申请人： STICHTING IMEC NEDERLAND

    发明人： Maryam Ashouei ,  Tobias Gemmeke

    IPC分类号： H03K19/003 ,  G01R17/02

    CPC分类号： H03K19/00384 ,  G01R17/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5002 ,  H03K19/0027 ,  H03K2217/0018

    摘要： The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.

    摘要翻译： 本公开涉及形成为集成电路的一部分的检测电路。 在一个示例中，检测电路包括被配置为产生参考信号的信号发生器和包括p沟道晶体管和n沟道晶体管的放大电路，其中放大电路受影响功能电路的可变性的影响 形成为集成电路的一部分。 可变性导致p沟道晶体管和n沟道晶体管具有不同的相应驱动强度。 放大电路被配置为接收参考信号并且提供表示各个驱动强度的差异的放大信号，其中参考信号对于可变性比放大的信号更不敏感。 本公开还涉及用于检测和补偿晶体管失配的集成电路和方法。

    ESD robust level shifter
    25.
    发明授权
    ESD robust level shifter 有权
    ESD鲁棒电平转换器

    公开(公告)号：US09154133B2

    公开(公告)日：2015-10-06

    申请号：US13630721

    申请日：2012-09-28

    申请人： Texas Instruments Incorporated

    发明人： Muhammad Yusuf Ali ,  Rajkumar Sankaralingam ,  Charles M. Branch

    IPC分类号： H03H9/46 ,  H03K19/003 ,  H02H9/04 ,  H01L27/02

    CPC分类号： H03K19/00384 ,  H01L27/0266 ,  H02H9/046

    摘要： An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

    摘要翻译： 逆变器型电平移位器包括第一电源电压和第一接地电压。 第一逆变器对第一电源电压和第一接地电压进行操作以产生第一逆变器输出。 第一反相器包括第一PMOS晶体管，其具有耦合到阻塞PMOS晶体管的源极的漏极和具有耦合到阻塞NMOS晶体管的源极的漏极的第一NMOS晶体管。 电平移位器还包括第二电源电压和第二接地电压，以及第二反相器，耦合到第一反相器输出并对第二电源电压和第二接地电压进行操作。 阻塞PMOS在第一电源电压的第二电源电压中的电压尖峰的事件上提供所需的阻塞，并且阻塞NMOS晶体管相对于第二电源电压在第二接地电压中的电压尖峰的事件上提供所需的阻塞 第一接地电压。

    Edge rate control gate drive circuit and system for low side devices with driver FET
    27.
    发明授权
    Edge rate control gate drive circuit and system for low side devices with driver FET 有权
    边沿速率控制栅极驱动电路和具有驱动器FET的低端器件的系统

    公开(公告)号：US09130560B2

    公开(公告)日：2015-09-08

    申请号：US13754468

    申请日：2013-01-30

    申请人： Texas Instruments Incorporated

    发明人： Adam L. Shook

    IPC分类号： H03K19/003 ,  G05F3/16 ,  H03K5/12

    CPC分类号： H03K19/00361 ,  G05F3/16 ,  H03K5/12 ,  H03K19/00384

    摘要： An apparatus, comprising a load; an output FET having a drain coupled to the load; a first and second of a pair strong FETs, wherein: a) a source of the first of the pair of the strong FETs is coupled to the load; b) a drain of the first pair of the strong FETs is coupled to the source of the second of the of the pair of the strong FETs; the drain of the second pair of the strong FETs is coupled to a gate of the output FET; and a fixed current mirror is coupled to the gate of the first of the pair of the strong FETs.

    摘要翻译： 一种装置，包括负载; 具有耦合到负载的漏极的输出FET; 第一和第二对强FET，其中：a）所述一对强FET中的第一个的源极耦合到所述负载; b）第一对强FET的漏极耦合到一对强FET中第二对的源的源极; 第二对强FET的漏极耦合到输出FET的栅极; 并且固定电流镜耦合到所述一对强FET中的第一对的栅极。