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公开(公告)号：US09991316B2
公开(公告)日：2018-06-05
申请号：US15374304
申请日：2016-12-09
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paola Zuliani , Gianluigi Confalonieri , Annalisa Gilardini , Carlo Luigi Prelini
CPC classification number: H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1683
Abstract: A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.
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公开(公告)号：US09882126B2
公开(公告)日：2018-01-30
申请号：US15095023
申请日：2016-04-09
Inventor： Matthew J. BrightSky , Huai-Yu Cheng , Wei-Chih Chien , Sangbum Kim , Chiao-Wen Yeh
CPC classification number: H01L45/1233 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/124 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.
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公开(公告)号：US20180017870A1
公开(公告)日：2018-01-18
申请号：US15547105
申请日：2015-04-27
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning GE , Zhiyong LI , Jianhua Yang , R. Stanley Williams
CPC classification number: G03F7/16 , B41J2/04541 , B41J2/04543 , B41J2/0458 , B41J2/14129 , B41J2202/13 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C19/28 , G11C2213/15 , G11C2213/31 , G11C2213/32 , H01L27/10817 , H01L27/2436 , H01L27/2463 , H01L28/87 , H01L28/91 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.
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公开(公告)号：US09847482B2
公开(公告)日：2017-12-19
申请号：US15305599
申请日：2014-04-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Hans S. Cho
CPC classification number: H01L45/1683 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1633 , H01L45/1658 , H01L45/1675
Abstract: A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region.
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25.再颁专利公开(公告)号：USRE46636E1
公开(公告)日：2017-12-12
申请号：US14836418
申请日：2015-08-26
Applicant: Sony Corporation
Inventor： Jun Sumino , Motonari Honda
CPC classification number: H01L45/1246 , H01L27/228 , H01L27/2436 , H01L27/2472 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
Abstract: A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.
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Patent Agency Ranking
公开(公告)号：US20170346003A1
公开(公告)日：2017-11-30
申请号：US15682040
申请日：2017-08-21
Applicant: Ovonyx Memory Technology, LLC
Inventor： Jun Liu
CPC classification number: H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
Abstract: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.
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公开(公告)号：US20170324034A1
公开(公告)日：2017-11-09
申请号：US15661351
申请日：2017-07-27
Applicant: Micron Technology, Inc.
Inventor： Eugene P. Marsh , Jun Liu
IPC: H01L45/00
CPC classification number: H01L45/085 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1253 , H01L45/1266 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
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公开(公告)号：US09799705B1
公开(公告)日：2017-10-24
申请号：US15297164
申请日：2016-10-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Liang Yi , Chia-Ching Hsu , Shen-De Wang , Ko-Chi Chen , Guoan Du
IPC: H01L45/00 , H01L27/24 , H01L21/768
CPC classification number: H01L27/2436 , H01L21/76877 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1608 , H01L45/1675 , H01L45/1683
Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.
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公开(公告)号：US20170301677A1
公开(公告)日：2017-10-19
申请号：US15477739
申请日：2017-04-03
Applicant: Western Digital Technologies, Inc.
Inventor： Mac D. APODACA , Daniel Robert SHEPARD
IPC: H01L27/112 , H01L27/115 , H01L27/108 , H01L29/10
CPC classification number: H01L27/249 , H01L27/10823 , H01L27/10864 , H01L27/10876 , H01L27/112 , H01L27/11521 , H01L27/11551 , H01L27/2427 , H01L27/2481 , H01L29/1037 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/1683
Abstract: The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4 F2 3D cross-point memory array has been formed.
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公开(公告)号：US20170294578A1
公开(公告)日：2017-10-12
申请号：US15095023
申请日：2016-04-09
Inventor： Matthew J. BrightSky , Huai-Yu Cheng , Wei-Chih Chien , Sangbum Kim , Chiao-Wen Yeh
CPC classification number: H01L45/1233 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/124 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.
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