公开(公告)号：US20030104651A1

公开(公告)日：2003-06-05

申请号：US10293933

申请日：2002-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woon-bae Kim ,  Hyung-jae Shin ,  Chang-ho Cho ,  Seung-goo Kang

IPC: H01L021/00 ,  H01L021/48 ,  H01L021/50 ,  H01L021/44 ,  H01L023/12

CPC classification number: B81C1/00269 ,  H01L21/50 ,  H01L23/10 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/163 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49789 ,  Y10T29/49794 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A hermetic sealing method, which is capable of preventing oxidation of a micro-electromechanical system (MEMS) and sealing the MEMS at a low temperature. A low temperature hermetic sealing method having a passivation layer includes depositing a junction layer, a wetting layer, and a solder layer on a prepared lid frame, depositing a first protection layer for preventing oxidation on the solder layer and forming a lid, preparing a package base on which a device is disposed, and in which a metal layer and a second protection layer are formed around the device, and assembling the lid and the package base, heating, and sealing them. The protection layer is laminated on the solder layer that is formed by the lid, thereby preventing oxidation without using a flux. The low temperature hermetic sealing method having a passivation layer is suitable for sealing a device, such as the MEMS, which is sensitive to heat, water and other by-products.

Abstract translation: 一种气密密封方法，其能够防止微机电系统（MEMS）的氧化并且在低温下密封MEMS。 具有钝化层的低温气密密封方法包括在准备的盖框架上沉积接合层，润湿层和焊料层，在焊料层上沉积防止氧化的第一保护层并形成盖子，制备封装 在其上设置器件，并且在器件周围形成金属层和第二保护层，并且组装盖子和封装基座，加热和密封它们。 保护层层压在由盖形成的焊料层上，从而防止氧化而不使用焊剂。 具有钝化层的低温气密密封方法适用于密封对热，水等副产物敏感的MEMS等装置。

公开(公告)号：US06414250B1

公开(公告)日：2002-07-02

申请号：US09752999

申请日：2000-12-30

Applicant: Hiroo Inoue ,  Michael Howieson ,  Mark Brooks

Inventor： Hiroo Inoue ,  Michael Howieson ,  Mark Brooks

IPC: H01R1204

CPC classification number: H01P3/081 ,  H01L23/10 ,  H01L2924/163 ,  H01L2924/3011 ,  H01P11/003 ,  H03H7/30 ,  H05K3/3405

Abstract: Thin film, multi-layered components wherein the layers are hermetically sealed with a re-flowed conductive sealant (e.g. Pb/Sn solder). The sealant is applied to an endless ground conductor at the peripheral edge of at least one of each pair of opposed substrate layers prior to registering the conductors and re-flowing the sealant. The microstrip conductors comprise thin film adhesion and seed layers and a covering metalization. The signal and ground conductors are terminated with solder balls and the signal and ground conductors are connected with micro vias that extend through the substrates.

Abstract translation: 薄膜，多层组分，其中层被再流动的导电密封剂（例如Pb / Sn焊料）气密密封。 在注入导体并重新流动密封剂之前，将密封剂施加到每对相对基板层中的至少一个的周边边缘处的环形接地导体。 微带导体包括薄膜粘合和种子层和覆盖金属化。 信号和接地导体用焊球端接，信号和接地导体与延伸穿过基板的微通孔连接。

公开(公告)号：US20020040808A1

公开(公告)日：2002-04-11

申请号：US09972920

申请日：2001-10-10

Inventor： Andreas Wilson ,  Hakan Bygdo

IPC: H05K001/00

CPC classification number: H05K9/0028 ,  H01L23/10 ,  H01L23/552 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/16315 ,  H01L2924/3025 ,  H05K3/1225 ,  H05K9/0015 ,  H01L2224/0401

Abstract: The invention relates to: A method of making a gasket (1) on a PCB (Printed Circuit Board) (2) and a PCB comprising a gasket. The object of the present invention is to provide a method of making a high quality gasket that may be conveniently customized to individual needs and which is easily integrated in a normal assembly process. The problem is solved in that the gasket (1) is made by screen printing techniques. This method has the advantage of using a technique that is already commonly used in an electronics assembly environment, and which method may implement relatively complex patterns with a relatively high precision in the layout of feature dimensions and which is relatively economic in use. The invention may e.g. be used for making customized gaskets for EMI shields on a PCB.

Abstract translation: 本发明涉及：在PCB（印刷电路板）（2）上制造衬垫（1）的方法和包括衬垫的PCB。 本发明的目的是提供一种制造高质量垫片的方法，其可以根据个别需要方便地定制，并且易于集成在正常组装过程中。 解决的问题是垫片（1）通过丝网印刷技术制成。 该方法具有使用电子装配环境中已经普遍使用的技术的优点，并且哪种方法可以在特征尺寸的布局中以相对较高的精度实现相对复杂的图案，并且在使用中相对经济。 本发明可以例如 用于在PCB上制作EMI屏蔽的定制垫圈。

公开(公告)号：US6037193A

公开(公告)日：2000-03-14

申请号：US792073

申请日：1997-01-31

Applicant: Mario J. Interrante ,  Laertis Economikos ,  Lester Wynn Herron

Inventor： Mario J. Interrante ,  Laertis Economikos ,  Lester Wynn Herron

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/28

CPC classification number: H01L23/10 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/163

Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.

Abstract translation: 本发明一般涉及一种使用低导热插入件及其结构对诸如氮化铝衬底的高导热衬底进行气密密封的新方法。 更具体地，本发明包括使用新型热插入件固定到氮化铝衬底的密封帽。 新型热插入件基本上由具有较高导热金属材料的层组成，夹层有低导热金属材料的芯层。

公开(公告)号：US5956576A

公开(公告)日：1999-09-21

申请号：US713378

申请日：1996-09-13

Applicant: Hilton T. Toy ,  Frank L. Pompeo

Inventor： Hilton T. Toy ,  Frank L. Pompeo

IPC: H01L23/10 ,  H01L21/44

CPC classification number: H01L23/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/16315 ,  H01L2924/166 ,  H01L2924/19105

Abstract: The present invention relates generally to a new apparatus and method for encapsulating ceramic chip carriers. More particularly, the invention encompasses an apparatus and a method for providing a fluid-tight, non-hermetic seal to a ceramic chip carrier utilizing dual surfaces. This is done by using the corner edges of the chip carrier, i.e., by using not only a minimal amount of the top-surface real estate of the chip carrier, but also the side-walls of the chip carrier to create the dual surface seal. This dual surface seal can be both hermetic and non-hermetic.

Abstract translation: 本发明一般涉及用于封装陶瓷芯片载体的新装置和方法。 更具体地说，本发明包括一种利用双重表面向陶瓷芯片载体提供流体密封的非气密密封的装置和方法。 这通过使用芯片载体的拐角边缘来完成，即，不仅使用最小量的芯片载体的顶表面空间，而且通过使用芯片载体的侧壁来产生双面密封 。 这种双面密封可以是密封的和非密封的。

公开(公告)号：US5784780A

公开(公告)日：1998-07-28

申请号：US778909

申请日：1997-01-03

Applicant: Mike C. Loo

Inventor： Mike C. Loo

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/055 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/055 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/30107 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate. Electrical continuity between the bottom surface of the z-conductive layer and the through-holes extending to the bottom surface of the substrate is substantially limited to the z axis of the z-conductive layer according to a predetermined pitch. A plurality of electrically conductive connectors are attached to the bottom surface of the z-conductive layer, and are disposed so as to be in electrical contact through the z-conductive layer with no more than one through-hole.

Abstract translation: 用于将半导体器件安装到电路板的封装。 提供了绝缘基板，其具有至少一层，并为封装提供刚性。 多个导电触点设置在基板的顶表面上，接收半导体器件，并在半导体器件和基板之间进行电接触。 多个导电通孔形成在基板中，并且从基板的顶表面延伸到基板的底表面。 通孔在基板的所有层之间形成电连接。 触点和通孔之间的电气互连由多个导电迹线提供。 z导电层附着到基底的底表面。 z导电层的底表面和延伸到衬底底表面的通孔之间的电连续性基本上以预定间距限制在z导电层的z轴上。 多个导电连接器附接到z导电层的底表面，并且设置成通过z导电层与不多于一个的通孔电接触。

公开(公告)号：US5744752A

公开(公告)日：1998-04-28

申请号：US464230

申请日：1995-06-05

Applicant: Dale C. McHerron ,  Hilton T. Toy

Inventor： Dale C. McHerron ,  Hilton T. Toy

IPC: H01L25/18 ,  H01L23/02 ,  H01L23/10 ,  H01L25/04

CPC classification number: H01L23/10 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166

Abstract: A module for encapsulating a microelectronic device has a polished mating surface around the periphery of the substrate on which is deposited at least one thin film sealband fabricated at a temperature no greater than about 400.degree. C. The sealband has a thickness of less than about 0.001 in. and comprising a metal capable of wetting molten solder which has a melting point no greater than about 400.degree. C. and adhering to the solder after solidification. A layer of the solder is disposed between the sealbands of the cap and substrate forming a hermetic seal for the module.

公开(公告)号：US5637920A

公开(公告)日：1997-06-10

申请号：US538631

申请日：1995-10-04

Applicant: Mike C. Loo

Inventor： Mike C. Loo

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/055 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/053 ,  H01L23/12

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/055 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/30107 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate. Electrical continuity between the bottom surface of the z-conductive layer and the through-holes extending to the bottom surface of the substrate is substantially limited to the z axis of the z-conductive layer according to a predetermined pitch. A plurality of electrically conductive connectors are attached to the bottom surface of the z-conductive layer, and are disposed so as to be in electrical contact through the z-conductive layer with no more than one through-hole.

Abstract translation: 用于将半导体器件安装到电路板的封装。 提供了绝缘基板，其具有至少一层，并为封装提供刚性。 多个导电触点设置在基板的顶表面上，接收半导体器件，并在半导体器件和基板之间进行电接触。 多个导电通孔形成在基板中，并且从基板的顶表面延伸到基板的底表面。 通孔在基板的所有层之间形成电连接。 触点和通孔之间的电气互连由多个导电迹线提供。 z导电层附着到基底的底表面。 z导电层的底表面和延伸到衬底底表面的通孔之间的电连续性基本上以预定间距限制在z导电层的z轴上。 多个导电连接器附接到z导电层的底表面，并且设置成通过z导电层与不多于一个的通孔电接触。

公开(公告)号：US5629835A

公开(公告)日：1997-05-13

申请号：US277387

申请日：1994-07-19

Applicant: Deepak Mahulikar ,  Paul R. Hoffman ,  Jeffrey S. Braden

Inventor： Deepak Mahulikar ,  Paul R. Hoffman ,  Jeffrey S. Braden

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/24 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H05K7/20 ,  H01L23/34

CPC classification number: H01L25/0657 ,  H01L21/4828 ,  H01L23/13 ,  H01L23/142 ,  H01L23/24 ,  H01L23/49816 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/181 ,  H01L2924/3025

Abstract: There is disclosed components for electronic packaging applications having integral bumps. A leadframe is formed by etching a metallic strip from one side to form outwardly extending, substantially perpendicular integral bumps. The metallic strip is then etched from the opposite side to form individual leads. When the integrally bumped component is an package base, fatigue of solder balls is reduced.

Abstract translation: 公开了具有整体凸块的用于电子封装应用的部件。 通过从一侧蚀刻金属带形成向外延伸的基本垂直的整体凸块来形成引线框架。 然后从相对侧蚀刻金属条形成单个引线。 当整体凸起的部件是封装基座时，焊球的疲劳减小。

公开(公告)号：US20180331089A1

公开(公告)日：2018-11-15

申请号：US16046859

申请日：2018-07-26

Applicant: Micron Technology, Inc.

Inventor： Rich Fogal ,  Owen R. Fay

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L21/48 ,  H01L21/54 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4817 ,  H01L21/54 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5386 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/8136 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/163 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/00012

Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.