公开(公告)号：US20240347458A1

公开(公告)日：2024-10-17

申请号：US18299043

申请日：2023-04-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHENG-FENG HUANG ,  JIANN-TYNG TZENG ,  SHIH-WEI PENG ,  YU-RONG CHEN

IPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L23/481 ,  H01L23/5226

摘要： A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a second electrical conductor, a third electrical conductor, a plurality of metal features and a plurality of active regions. The first electrical conductor extends along a first direction and is electrically coupled to a first voltage. The second electrical conductor extends along the first direction and is electrically coupled to a second voltage. The second voltage is lower than the first voltage. The third electrical conductor extending along the first direction is electrically coupled to a third voltage and disposed between the first electrical conductor and the second electrical conductor. The metal features extend along a second direction perpendicular to the first direction and are formed above the first electrical conductor, the second electrical conductor and the third electrical conductor.

公开(公告)号：US20240347447A1

公开(公告)日：2024-10-17

申请号：US18751362

申请日：2024-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/05 ,  H01L25/0657

摘要： A method of forming a semiconductor package includes the following steps. A first die is provided, wherein the first die comprises a plurality of first conductive patterns. A plurality of second conductive patterns are formed over the first die, wherein the second conductive patterns are connected to the first conductive patterns to form a first coil and a second coil surrounding the first coil.

公开(公告)号：US20240347444A1

公开(公告)日：2024-10-17

申请号：US18135319

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PIN-JHU LI ,  SHIH-FAN KUAN

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76883 ,  H01L28/87 ,  H01L28/91

摘要： A conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. The conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. The second support layer is disposed over the first support layer. The first conductive via is disposed between the first support layer and the second support layer. The third support layer is disposed over the second support layer. The second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. A lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.

公开(公告)号：US12120877B2

公开(公告)日：2024-10-15

申请号：US17693328

申请日：2022-03-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jinyoung Park ,  Hyuk Kim ,  Yeongeun Yook

IPC分类号： H10B43/27 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC分类号： H10B43/27 ,  G11C5/06 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

摘要： A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

申请人： Socionext Inc.

发明人： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L23/5226

摘要： A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20240339513A1

公开(公告)日：2024-10-10

申请号：US18748250

申请日：2024-06-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC分类号： H01L29/417 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L29/41791 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/401

摘要： An exemplary semiconductor device includes a substrate, a first conductive feature, a second conductive feature, and a third conductive feature over the substrate. The first conductive feature has a first top surface and a side surface. The third conductive feature is on the first top surface of the first conductive feature and is spaced away from the second conductive feature. The third conductive feature has a first sidewall and a second sidewall opposing the first sidewall. The first sidewall extends between the first conductive feature and the second conductive feature. At least a segment of the first sidewall has a first slope. The second sidewall has a second slope. The second slope is greater than the first slope.

公开(公告)号：US20240339407A1

公开(公告)日：2024-10-10

申请号：US18607380

申请日：2024-03-15

申请人： Destination 2D Inc.

发明人： Klaus SCHUEGRAF ,  Kaustav BANERJEE ,  Brian CRONQUIST

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/53276 ,  H01L23/5226 ,  H01L23/5283

摘要： An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.

公开(公告)号：US20240339402A1

公开(公告)日：2024-10-10

申请号：US18382251

申请日：2023-10-20

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhong ZHANG ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

摘要： A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

公开(公告)号：US20240339397A1

公开(公告)日：2024-10-10

申请号：US18746055

申请日：2024-06-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

摘要： An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US12113034B2

公开(公告)日：2024-10-08

申请号：US18138865

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chien-Hsuan Liu

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/585 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5283

摘要： A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.