公开(公告)号：US20210020571A1

公开(公告)日：2021-01-21

申请号：US17063452

申请日：2020-10-05

申请人： SOCIONEXT INC.

发明人： Atsushi Okamoto ,  Hirotaka Takeno

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687

摘要： A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.

公开(公告)号：US20180315743A1

公开(公告)日：2018-11-01

申请号：US15953899

申请日：2018-04-16

申请人： Socionext Inc.

发明人： Hirotaka Takeno ,  Atsushi Okamoto

IPC分类号： H01L27/02 ,  H03K17/16 ,  H01L23/528 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L21/823892 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/785 ,  H01L2027/11875 ,  H01L2027/11881 ,  H03K17/161 ,  H03K19/0016

摘要： A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US20190312024A1

公开(公告)日：2019-10-10

申请号：US16448241

申请日：2019-06-21

申请人： Socionext Inc.

发明人： Hirotaka Takeno ,  Atsushi Okamoto

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/092 ,  H01L29/10 ,  H03K17/16 ,  H01L29/08 ,  H03K19/00 ,  H01L21/8238

摘要： A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US12068288B2

公开(公告)日：2024-08-20

申请号：US18179013

申请日：2023-03-06

申请人： SOCIONEXT INC.

发明人： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L27/088

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

摘要： A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US11563432B2

公开(公告)日：2023-01-24

申请号：US17577701

申请日：2022-01-18

申请人： Socionext Inc.

发明人： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC分类号： H03K17/00 ,  H03K17/16 ,  H03K17/687

摘要： A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11309248B2

公开(公告)日：2022-04-19

申请号：US17063452

申请日：2020-10-05

申请人： SOCIONEXT INC.

发明人： Atsushi Okamoto ,  Hirotaka Takeno

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687

摘要： A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.

公开(公告)号：US11233044B2

公开(公告)日：2022-01-25

申请号：US17014662

申请日：2020-09-08

申请人： SOCIONEXT INC.

发明人： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L23/522

摘要： A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US10734373B2

公开(公告)日：2020-08-04

申请号：US16189900

申请日：2018-11-13

申请人： SOCIONEXT INC.

发明人： Atsushi Okamoto ,  Tomoyasu Kitaura ,  Hirotaka Takeno

IPC分类号： H01L27/02 ,  G06F1/26 ,  H01L27/118 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H03K19/00

摘要： A circuit block including standard cells (1) arranged therein is provided with switch cells (20) capable of switching between electrical connection and disconnection between power supply lines (3) extending in an X-direction and power supply straps (11) extending in a Y-direction. Each of the power supply straps (11) is provided with a single switch cell (20) arranged every M sets of power supply lines (3) (M is an integer of 3 or more). In the Y-direction, the switch cells (20) are arranged at different positions in the power supply straps (11) adjacent to each other, and are arranged at the same position every M power supply straps (11) in the X-direction.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

申请人： Socionext Inc.

发明人： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L23/5226

摘要： A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US12087735B2

公开(公告)日：2024-09-10

申请号：US17210743

申请日：2021-03-24

申请人： SOCIONEXT INC.

发明人： Hirotaka Takeno ,  Wenzhen Wang ,  Atsushi Okamoto

IPC分类号： H01L25/065 ,  G11C5/14 ,  H01L27/02 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L27/0207 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544

摘要： A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.