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    VERTICAL MEMORY DEVICE
    1.
    发明申请
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20190259881A1

    公开(公告)日：2019-08-22

    申请号：US16400443

    申请日：2019-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung II Cho

    IPC: H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11556

    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

    Vertical memory device
    2.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US10319864B2

    公开(公告)日：2019-06-11

    申请号：US15849094

    申请日：2017-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung Il Cho

    IPC: H01L21/28 ,  H01L29/10 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11578

    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

    Shrouds and substrate treating systems including the same
    5.
    发明授权
    Shrouds and substrate treating systems including the same 有权

    公开(公告)号：US10950419B2

    公开(公告)日：2021-03-16

    申请号：US15945001

    申请日：2018-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Edward Sung ,  Hyuk Kim ,  Daehyun Jang ,  Sung Il Cho

    IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

    Abstract: Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.

    Plasma treatment apparatus and method of fabricating semiconductor device using the same
    6.
    发明授权
    Plasma treatment apparatus and method of fabricating semiconductor device using the same 有权

    公开(公告)号：US10790168B2

    公开(公告)日：2020-09-29

    申请号：US15972350

    申请日：2018-05-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Bo Shim ,  Hyuk Kim ,  Sun Taek Lim ,  Jae Myung Choe ,  Jeon Il Lee ,  Sung-Il Cho

    IPC: H01L21/67 ,  H01L21/683 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/311

    Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

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