公开(公告)号：US10749042B2

公开(公告)日：2020-08-18

申请号：US16400443

申请日：2019-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung II Cho

IPC: H01L29/792 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

公开(公告)号：US20190259881A1

公开(公告)日：2019-08-22

申请号：US16400443

申请日：2019-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung II Cho

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11556

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

公开(公告)号：US10319864B2

公开(公告)日：2019-06-11

申请号：US15849094

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung Il Cho

IPC: H01L21/28 ,  H01L29/10 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11578

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.