公开(公告)号：US20240339397A1

公开(公告)日：2024-10-10

申请号：US18746055

申请日：2024-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US20230215801A1

公开(公告)日：2023-07-06

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US10600732B1

公开(公告)日：2020-03-24

申请号：US16122807

申请日：2018-09-05

Applicant: United Microelectronics Corp.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Yi-Hsiu Chen ,  Chih-Sheng Chang

IPC: H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.

公开(公告)号：US12154852B2

公开(公告)日：2024-11-26

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US20210159170A1

公开(公告)日：2021-05-27

申请号：US16709934

申请日：2019-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.

公开(公告)号：US11646264B2

公开(公告)日：2023-05-09

申请号：US17168099

申请日：2021-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/033

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/7684 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5283

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.

公开(公告)号：US20220216144A1

公开(公告)日：2022-07-07

申请号：US17168099

申请日：2021-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.

公开(公告)号：US11127675B2

公开(公告)日：2021-09-21

申请号：US16709934

申请日：2019-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.

公开(公告)号：US20200075480A1

公开(公告)日：2020-03-05

申请号：US16122807

申请日：2018-09-05

Applicant: United Microelectronics Corp.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Yi-Hsiu Chen ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.

公开(公告)号：US10204826B1

公开(公告)日：2019-02-12

申请号：US15893711

申请日：2018-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/321

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.