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195 条记录 (耗时 0.029 秒)

    Single electron resistor memory device and method
    21.
    发明授权
    Single electron resistor memory device and method 有权

    公开(公告)号：US06452831B2

    公开(公告)日：2002-09-17

    申请号：US09944258

    申请日：2001-08-29

    申请人： Kie Y. Ahn ,  Leonard Forbes

    发明人： Kie Y. Ahn ,  Leonard Forbes

    IPC分类号： G11C1100

    CPC分类号： G11C16/04 ,  B82Y10/00 ,  G11C11/34 ,  G11C16/0416 ,  G11C2216/08 ,  H01L29/7888 ,  Y10S977/937

    摘要： A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

    Semiconductor integrated circuit and nonvolatile memory element
    22.
    发明申请
    Semiconductor integrated circuit and nonvolatile memory element 有权
    半导体集成电路和非易失性存储元件

    公开(公告)号：US20020126521A1

    公开(公告)日：2002-09-12

    申请号：US09942902

    申请日：2001-08-31

    发明人： Shoji Shukuri ,  Kazuhiro Komori ,  Katsuhiko Kubota ,  Kousuke Okuyama

    IPC分类号： G11C011/22

    CPC分类号： H01L27/11526 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28 ,  G11C16/349 ,  G11C2216/08 ,  G11C2216/10 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

    摘要： An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

    摘要翻译： 基于包含一对差分形式的非易失性存储器元件的存储器单元的信息保持能力得到改善。 构成闪速存储器的非易失性存储元件（130）被构造成通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）分别形成隧道氧化物膜（GO3）和浮栅电极（FGT） 用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。 存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态 以便差异地读出数据。 读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值 电压值。 因此，增强数据保持能力以实现读出故障率的降低。

    Single electron MOSFET memory device and method
    25.
    发明授权
    Single electron MOSFET memory device and method 失效
    单电子MOSFET存储器件及方法

    公开(公告)号：US06297994B1

    公开(公告)日：2001-10-02

    申请号：US09619177

    申请日：2000-07-19

    申请人： Kie Ahn ,  Leonard Forbes

    发明人： Kie Ahn ,  Leonard Forbes

    IPC分类号： G11C1604

    CPC分类号： B82Y10/00 ,  G11C11/34 ,  G11C11/40 ,  G11C11/404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/108 ,  H01L29/7888 ,  Y10S438/962 ,  Y10S977/937

    摘要： A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

    摘要翻译： 描述了存储器件和相关方法。 存储器件包括多个单元，每个单元包括一个具有耦合到沟道第一端的源极的MOSFET，耦合到沟道的第二端的漏极，形成在栅极绝缘体上并从源极延伸到 漏极和形成在通道中的多个由绝缘体包围的导电岛。 岛屿的最大尺寸为三纳米。 周围绝缘体的厚度介于5至20纳米之间。 每个岛和周围的绝缘体形成在延伸到通道中的孔中。 结果，存储器单元能够响应于岛上存在或不存在单个电子而提供一致的外部可观察到的变化。

    Semiconductor memory device
    27.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06194759B1

    公开(公告)日：2001-02-27

    申请号：US09436225

    申请日：1999-11-09

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L2976

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

    Differential flash memory cell and method for programming same
    28.
    发明授权
    Differential flash memory cell and method for programming same 有权
    差分闪存单元和编程方法相同

    公开(公告)号：US6141256A

    公开(公告)日：2000-10-31

    申请号：US470079

    申请日：1999-12-22

    申请人： Leonard Forbes

    发明人： Leonard Forbes

    IPC分类号： B82B1/00 ,  G11C11/56 ,  G11C16/04 ,  G11C7/00

    CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0441 ,  G11C2211/5612 ,  G11C2216/08

    摘要： A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores a programmed state of the second transistor. A difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.

    摘要翻译： 闪存单元。 闪存单元包括第一和第二晶体管。 第一晶体管具有耦合到字线的控制栅极，耦合到数据线的漏极和浮置栅极。 类似地，第二晶体管包括耦合到字线的控制栅极，耦合到第二数据线的漏极和第二浮置栅极。 在闪存单元的编程之前，第一浮动栅极存储第二晶体管的状态。 此外，第二浮动栅极存储第二晶体管的编程状态。 第一和第二晶体管的状态之间的差异代表存储在闪存单元中的数据的值。

    Semiconductor memory device
    29.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6040605A

    公开(公告)日：2000-03-21

    申请号：US236630

    申请日：1999-01-26

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  G11C2216/08

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。