知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.068 seconds)

    CROSS-POINT ARCHITECTURE FOR PCRAM
    26.
    发明公开
    CROSS-POINT ARCHITECTURE FOR PCRAM 审中-公开

    公开(公告)号：US20230380194A1

    公开(公告)日：2023-11-23

    申请号：US17751638

    申请日：2022-05-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Pin Chang ,  Kuo-Ching Huang

    IPC: H01L27/24 ,  H01L45/00 ,  G11C5/06

    CPC classification number: H01L27/249 ,  H01L27/2436 ,  H01L45/06 ,  G11C5/063 ,  H01L45/1608

    Abstract: A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row and the memory cells in the second row are disposed on the first common word line metal track; and a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells.

    ANTI-FERROELECTRIC TUNNEL JUNCTION WITH ASYMMETRICAL METAL ELECTRODES
    28.
    发明申请
    ANTI-FERROELECTRIC TUNNEL JUNCTION WITH ASYMMETRICAL METAL ELECTRODES 有权

    公开(公告)号：US20230011305A1

    公开(公告)日：2023-01-12

    申请号：US17690685

    申请日：2022-03-09

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuen-Yi Chen ,  Yi-Hsuan Chen ,  Yi Ching Ong ,  Kuo-Ching Huang

    IPC: H01L27/11507

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect wires and vias arranged within one or more interconnect dielectric layers over a substrate. Further, a bottom electrode is disposed over the one or more interconnect wires and vias and comprises a first material having a first work function. A top electrode is disposed over the bottom electrode and comprises a second material having a second work function. The first material is different than the second material, and the first work function is different than the second work function. An anti-ferroelectric layer is disposed between the top and bottom electrodes.

    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING
    29.
    发明申请
    HIGH ELECTRON AFFINITY DIELECTRIC LAYER TO IMPROVE CYCLING 有权

    公开(公告)号：US20220384724A1

    公开(公告)日：2022-12-01

    申请号：US17880835

    申请日：2022-08-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

Patent Agency Ranking