公开(公告)号：US20240162083A1

公开(公告)日：2024-05-16

申请号：US18421155

申请日：2024-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chen-Han WANG ,  Keng-Chu LIN ,  Tetsuji UENO ,  Ting-Ting CHEN

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76832 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6653

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

公开(公告)号：US20230386912A1

公开(公告)日：2023-11-30

申请号：US18232718

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L23/5226 ,  H01L23/53266 ,  H01L21/76816 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76876

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

公开(公告)号：US20230369335A1

公开(公告)日：2023-11-16

申请号：US18358312

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

公开(公告)号：US20230061022A1

公开(公告)日：2023-03-02

申请号：US17459799

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Kai CHANG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

公开(公告)号：US20230047641A1

公开(公告)日：2023-02-16

申请号：US17654886

申请日：2022-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yu YEN ,  Ko-Feng CHEN ,  Keng-Chu LIN

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes (i) a first epitaxial structure embedded in the substrate; (ii) a nitride layer on the first epitaxial structure; and a second epitaxial structure on the first epitaxial structure. The semiconductor device also includes a gate structure formed on the nanostructures.

公开(公告)号：US20230009077A1

公开(公告)日：2023-01-12

申请号：US17681346

申请日：2022-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Huan-Chieh SU ,  Lo-Heng CHANG ,  Shih-Chuan CHIU ,  Hsu-Kai CHANG ,  Ko-Feng CHEN ,  Keng-Chu LIN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second contact openings on the n- and p-type S/D regions, respectively, forming a carbon-based layer in the first and second contact openings, performing a remote plasma treatment with radicals on the carbon-based layer to form a remote plasma treated layer, selectively removing a portion of the remote plasma treated layer, forming a p-type work function metal (pWFM) silicide layer on the p-type S/D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and on the n-type S/D region.

公开(公告)号：US20210376103A1

公开(公告)日：2021-12-02

申请号：US16887577

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US20210226057A1

公开(公告)日：2021-07-22

申请号：US16744480

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

公开(公告)号：US20210184018A1

公开(公告)日：2021-06-17

申请号：US16717600

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. KHADERBAD ,  Keng-Chu LIN

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/768

Abstract: The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.

公开(公告)号：US20190103485A1

公开(公告)日：2019-04-04

申请号：US16053656

申请日：2018-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/308

Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.