公开(公告)号：US11158727B2

公开(公告)日：2021-10-26

申请号：US16509184

申请日：2019-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Chun-Hsiung Lin ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06

Abstract: The present disclosure provides a method of semiconductor fabrication that includes forming a semiconductor fin protruding from a substrate, the semiconductor fin including a plurality of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked, the second semiconductor material being different from the first semiconductor material in composition; forming a first gate stack on the semiconductor fin; forming a recess in the semiconductor fin within a source/drain (S/D) region adjacent to the first gate stack, a sidewall of the first and second semiconductor material layers being exposed within the recess; performing an etching process to the semiconductor fin, resulting in an undercut below the first gate stack; epitaxially growing on the sidewall of the semiconductor fin to fill in the undercut with a semiconductor extended feature of the first semiconductor material; and growing an epitaxial S/D feature from the recess.

公开(公告)号：US10944009B2

公开(公告)日：2021-03-09

申请号：US16582547

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate; an isolation structure at least partially surrounding the fin; an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein an extended portion of the epitaxial S/D feature extends over the isolation structure; and a silicide layer disposed on the epitaxial S/D feature, the silicide layer continuously surrounding the extended portion of the epitaxial S/D feature over the isolation structure.

公开(公告)号：US10804162B2

公开(公告)日：2020-10-13

申请号：US16366946

申请日：2019-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/306 ,  H01L21/311 ,  H01L21/027 ,  H01L21/762 ,  H01L29/66

Abstract: A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.

公开(公告)号：US10727134B2

公开(公告)日：2020-07-28

申请号：US16284113

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Chih-Hao Wang ,  Chih-Chao Chou

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure.

公开(公告)号：US12198986B2

公开(公告)日：2025-01-14

申请号：US18366562

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Sheng Yun ,  Chih-Hao Wang ,  Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Chun-Hsiung Lin ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

公开(公告)号：US11996483B2

公开(公告)日：2024-05-28

申请号：US18066141

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US11916125B2

公开(公告)日：2024-02-27

申请号：US17871509

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US20230013764A1

公开(公告)日：2023-01-19

申请号：US17683944

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Min Cao

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/528

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

公开(公告)号：US20220328363A1

公开(公告)日：2022-10-13

申请号：US17358985

申请日：2021-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L23/50 ,  H01L21/768

Abstract: Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.

公开(公告)号：US11251090B2

公开(公告)日：2022-02-15

申请号：US16737591

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/306 ,  H01L21/311 ,  H01L21/027 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.