公开(公告)号：US20220293759A1

公开(公告)日：2022-09-15

申请号：US17199629

申请日：2021-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US20220181259A1

公开(公告)日：2022-06-09

申请号：US17682701

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Chih-Chao Chou ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L23/528 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

摘要： Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

公开(公告)号：US11342325B2

公开(公告)日：2022-05-24

申请号：US16823581

申请日：2020-03-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Wen-Ting Lan

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.

公开(公告)号：US10833003B1

公开(公告)日：2020-11-10

申请号：US16427831

申请日：2019-05-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Ching ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L23/50 ,  H01L27/088 ,  H01L29/78

摘要： Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US20200105617A1

公开(公告)日：2020-04-02

申请号：US16366946

申请日：2019-03-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Pei-Hsun Wang

IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

摘要： A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.

公开(公告)号：US20240363522A1

公开(公告)日：2024-10-31

申请号：US18768225

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L23/50 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L23/50 ,  H01L27/0886 ,  H01L29/785

摘要： Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US20240250141A1

公开(公告)日：2024-07-25

申请号：US18588727

申请日：2024-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US11695076B2

公开(公告)日：2023-07-04

申请号：US17193732

申请日：2021-03-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC分类号： H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US20230145872A1

公开(公告)日：2023-05-11

申请号：US18066141

申请日：2022-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC分类号： H01L29/78618 ,  H01L29/0673 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/78684

摘要： The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US11444170B1

公开(公告)日：2022-09-13

申请号：US17199629

申请日：2021-03-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.