公开(公告)号：US20240363522A1

公开(公告)日：2024-10-31

申请号：US18768225

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/50 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/50 ,  H01L27/0886 ,  H01L29/785

Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

公开(公告)号：US20240250141A1

公开(公告)日：2024-07-25

申请号：US18588727

申请日：2024-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US11695076B2

公开(公告)日：2023-07-04

申请号：US17193732

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US20230145872A1

公开(公告)日：2023-05-11

申请号：US18066141

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L29/0673 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/78684

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US11444170B1

公开(公告)日：2022-09-13

申请号：US17199629

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US20210296312A1

公开(公告)日：2021-09-23

申请号：US16823581

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Wen-Ting Lan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.

公开(公告)号：US11031481B2

公开(公告)日：2021-06-08

申请号：US17001501

申请日：2020-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Lin ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Chih-Chao Chou ,  Pei-Yu Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20250087632A1

公开(公告)日：2025-03-13

申请号：US18405718

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Ching-Wei Tsai ,  Yi-Hsun Chiu

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. The through via is disposed outside of and adjacent to the second semiconductor die. The through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.

公开(公告)号：US12183678B2

公开(公告)日：2024-12-31

申请号：US18499481

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Chih-Chao Chou ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

公开(公告)号：US20220293759A1

公开(公告)日：2022-09-15

申请号：US17199629

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.