-
公开(公告)号：US20230188159A1
公开(公告)日：2023-06-15
申请号：US18165025
申请日：2023-02-06
Inventor： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC classification number: H03M7/16 , G11C11/1673 , H03K19/20
Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
-
22.发明授权公开(公告)号：US11657873B2
公开(公告)日：2023-05-23
申请号：US17409341
申请日：2021-08-23
Inventor： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC: G11C14/00 , G11C11/419 , G11C11/16
CPC classification number: G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
-
公开(公告)号：US20230057357A1
公开(公告)日：2023-02-23
申请号：US17407451
申请日：2021-08-20
Inventor： Ku-Feng Lin , Jui-Che Tsai , Perng-Fei Yuh , Yih Wang
Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
-
公开(公告)号：US11574657B2
公开(公告)日：2023-02-07
申请号：US17035609
申请日：2020-09-28
Inventor： Ku-Feng Lin
IPC: G11C7/06
Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.
-
公开(公告)号：US11380371B2
公开(公告)日：2022-07-05
申请号：US17096966
申请日：2020-11-13
Inventor： Ku-Feng Lin , Yu-Der Chih
Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.
-
Patent Agency Ranking
公开(公告)号：US09673799B2
公开(公告)日：2017-06-06
申请号：US14942372
申请日：2015-11-16
Inventor： Ku-Feng Lin , Hung-Chang Yu
CPC classification number: H03K5/2481 , G11C7/062 , G11C13/004 , G11C2013/0054
Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.
-
公开(公告)号：US20150063048A1
公开(公告)日：2015-03-05
申请号：US14016917
申请日：2013-09-03
Inventor： Ku-Feng Lin , Hung-Chang Yu , Yue-Der Chih
CPC classification number: G11C7/062 , G11C7/067 , G11C7/08 , G11C27/02 , G11C2207/063
Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
Abstract translation: 器件包括放大器和第一开关电流采样器。 第一开关电流采样器包括第一晶体管，第一电容器以及第一，第二和第三开关。 第一电容器具有电连接到第一晶体管的栅电极的第一端子和与第一晶体管的源电极电连接的第二端子。 第一开关具有电连接到第一电流源的第一端子和电连接到第一晶体管的栅电极的第二端子。 第二开关具有电连接到第一电流源的第一端子和与第一晶体管的漏电极电连接的第二端子。 第三开关具有电连接到第一晶体管的漏电极的第一端子和与放大器的第一输入端子电连接的第二端子。
-
公开(公告)号：US12288577B2
公开(公告)日：2025-04-29
申请号：US18177749
申请日：2023-03-02
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
-
公开(公告)号：US12284804B2
公开(公告)日：2025-04-22
申请号：US18404849
申请日：2024-01-04
Inventor： Perng-Fei Yuh , Yih Wang , Meng-Sheng Chang , Jui-Che Tsai , Ku-Feng Lin , Yu-Wei Lin , Keh-Jeng Chang , Chansyun David Yang , Shao-Ting Wu , Shao-Yu Chou , Philex Ming-Yan Fan , Yoshitaka Yamauchi , Tzu-Hsien Yang
Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
-
公开(公告)号：US20240356562A1
公开(公告)日：2024-10-24
申请号：US18635948
申请日：2024-04-15
Inventor： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC classification number: H03M7/16 , G11C11/1673 , H03K19/20
Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
-
-
-
-
-
-
-
-
-
Search Results
73
records
(took 0.022 seconds)
