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    MAINTAINING PHASE COHERENCE FOR A FRACTIONAL-N PLL
    21.
    发明申请
    MAINTAINING PHASE COHERENCE FOR A FRACTIONAL-N PLL 有权

    公开(公告)号：US20240429926A1

    公开(公告)日：2024-12-26

    申请号：US18821040

    申请日：2024-08-30

    Applicant: Silicon Laboratories Inc.

    Inventor： John M. Khoury ,  Michael Wu

    IPC: H03L7/099 ,  H03B5/32

    Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.

    Maintaining phase coherence for a fractional-N PLL
    22.
    发明授权
    Maintaining phase coherence for a fractional-N PLL 有权

    公开(公告)号：US12107588B2

    公开(公告)日：2024-10-01

    申请号：US18076058

    申请日：2022-12-06

    Applicant: Silicon Laboratories Inc.

    Inventor： John M. Khoury ,  Michael Wu

    IPC: H03L7/099 ,  H03B5/32

    CPC classification number: H03L7/0991 ,  H03B5/32

    Abstract: A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.

    PHASE MEASUREMENTS FOR HIGH ACCURACY DISTANCE MEASUREMENTS
    26.
    发明申请
    PHASE MEASUREMENTS FOR HIGH ACCURACY DISTANCE MEASUREMENTS 有权

    公开(公告)号：US20220174632A1

    公开(公告)日：2022-06-02

    申请号：US17107281

    申请日：2020-11-30

    Applicant: Silicon Laboratories Inc.

    Inventor： John M. Khoury ,  Yan Zhou ,  Michael A. Wu

    IPC: H04W56/00

    Abstract: In at least one embodiment, a method for measuring a distance between a first communications device including a first local oscillator and a second communications device including a second local oscillator includes unwrapping N phase values to generate N unwrapped phase values. N is an integer greater than one. Each of the N phase values indicate an instantaneous phase of a received signal. The method includes averaging the N unwrapped phase values to generate an average phase value. The method includes wrapping the average phase value to generate a final phase measurement of the first local oscillator with respect to the second local oscillator.

    LOW POWER WAKE ON RADIO
    28.
    发明申请
    LOW POWER WAKE ON RADIO 有权

    公开(公告)号：US20210282088A1

    公开(公告)日：2021-09-09

    申请号：US17329496

    申请日：2021-05-25

    Applicant: Silicon Laboratories Inc.

    Inventor： Pio Balmelli ,  Praveen Vangala ,  John M. Khoury

    IPC: H04W52/02

    Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

    Apparatus for Digital Phase-Locked Loop and Associated Methods
    29.
    发明申请
    Apparatus for Digital Phase-Locked Loop and Associated Methods 审中-公开

    公开(公告)号：US20190268008A1

    公开(公告)日：2019-08-29

    申请号：US15904173

    申请日：2018-02-23

    Applicant: Silicon Laboratories Inc.

    Inventor： John M. Khoury ,  Peijun Wang

    IPC: H03L7/099 ,  H03L7/24 ,  G01K7/02

    Abstract: An apparatus includes a digital phase-locked loop (DPLL). The DPLL includes a digital phase and frequency detector coupled to receive a reference signal and to generate a first set of output signals, and a digital loop filter that receives the first set of output signals of the phase and frequency detector output and generates an integral path control signal and a proportional path control signal. The DPLL further includes a digital to analog converter (DAC) to convert the integral path control signal and the proportional path control signal to a second set of output signals. The DPLL in addition includes a controlled oscillator (CO) to generate an output signal in response to the second set of output signals.

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