公开(公告)号：US20190268008A1

公开(公告)日：2019-08-29

申请号：US15904173

申请日：2018-02-23

Applicant: Silicon Laboratories Inc.

Inventor： John M. Khoury ,  Peijun Wang

IPC: H03L7/099 ,  H03L7/24 ,  G01K7/02

Abstract: An apparatus includes a digital phase-locked loop (DPLL). The DPLL includes a digital phase and frequency detector coupled to receive a reference signal and to generate a first set of output signals, and a digital loop filter that receives the first set of output signals of the phase and frequency detector output and generates an integral path control signal and a proportional path control signal. The DPLL further includes a digital to analog converter (DAC) to convert the integral path control signal and the proportional path control signal to a second set of output signals. The DPLL in addition includes a controlled oscillator (CO) to generate an output signal in response to the second set of output signals.