公开(公告)号：US11195822B2

公开(公告)日：2021-12-07

申请号：US16862648

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Joon Pyeon ,  Changhoon Kwak ,  Moonsub Kim ,  Sangsu Kim ,  Myoungsun Ha

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/54

Abstract: A light-emitting package including a substrate having pixel regions; first to third light-emitting chips on each of the pixel regions; and a molding layer on a top surface of the substrate, the molding layer covering the first to third light-emitting chips, wherein one of the first to third light-emitting chips emits light whose color is different from others of the first to third light-emitting chips, on pixel regions, the first to third light-emitting chips are arranged along a first direction, the first direction being parallel to the top surface of the substrate, a minimum interval between the first light-emitting chip and a top or side surface of the molding layer is different from a minimum interval between the second light-emitting chip and the top or side surface of the molding layer, the side surface of the molding layer intersects a second direction parallel to the top surface of the substrate.

公开(公告)号：US20210066260A1

公开(公告)日：2021-03-04

申请号：US16862648

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Joon Pyeon ,  Changhoon Kwak ,  Moonsub Kim ,  Sangsu Kim ,  Myoungsun Ha

IPC: H01L25/075 ,  H01L33/54 ,  H01L33/62

Abstract: A light-emitting package including a substrate having pixel regions; first to third light-emitting chips on each of the pixel regions; and a molding layer on a top surface of the substrate, the molding layer covering the first to third light-emitting chips, wherein one of the first to third light-emitting chips emits light whose color is different from others of the first to third light-emitting chips, on pixel regions, the first to third light-emitting chips are arranged along a first direction, the first direction being parallel to the top surface of the substrate, a minimum interval between the first light-emitting chip and a top or side surface of the molding layer is different from a minimum interval between the second light-emitting chip and the top or side surface of the molding layer, the side surface of the molding layer intersects a second direction parallel to the top surface of the substrate.

公开(公告)号：US20210036121A1

公开(公告)日：2021-02-04

申请号：US16822275

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmook Lim ,  Sangsu Kim ,  Wooseok Park ,  Daekwon Joo

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088

Abstract: A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.

公开(公告)号：US09711506B2

公开(公告)日：2017-07-18

申请号：US15249518

申请日：2016-08-29

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/306 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US09679975B2

公开(公告)日：2017-06-13

申请号：US14823229

申请日：2015-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC: H01L31/00 ,  H01L29/74 ,  H01L23/52 ,  H01L29/66 ,  H01L29/267 ,  H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.