公开(公告)号：US20250089299A1

公开(公告)日：2025-03-13

申请号：US18960679

申请日：2024-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbeom Park ,  Sangsu Kim ,  Junggil Yang

IPC: H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

公开(公告)号：US10177150B2

公开(公告)日：2019-01-08

申请号：US15615643

申请日：2017-06-06

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/423 ,  H01L29/10

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US20160268394A1

公开(公告)日：2016-09-15

申请号：US15165931

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

公开(公告)号：US12183796B2

公开(公告)日：2024-12-31

申请号：US17189615

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbeom Park ,  Sangsu Kim ,  Junggil Yang

IPC: H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

公开(公告)号：US20210217848A1

公开(公告)日：2021-07-15

申请号：US16943103

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu Kim ,  Junbeom Park ,  Junggil Yang

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

公开(公告)号：US09287401B2

公开(公告)日：2016-03-15

申请号：US14469615

申请日：2014-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan Lee ,  Sangsu Kim ,  Changjae Yang

IPC: H01L21/76 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/785

Abstract: A field effect transistor includes a fin structure, having a sidewall, protruding from a substrate, and a device isolation structure on the substrate, the device isolation structure defining the sidewall of the fin structure, wherein the fin structure includes a buffer semiconductor pattern disposed on the substrate and a channel pattern disposed on the buffer semiconductor pattern, wherein the buffer semiconductor pattern has a lattice constant different from that of the channel pattern, and wherein the device isolation structure includes a gap-fill insulating layer, and includes an oxidation blocking layer pattern disposed between the buffer semiconductor pattern and the gap-fill insulating layer.

Abstract translation: 场效应晶体管包括翅片结构，其具有从衬底突出的侧壁和衬底上的器件隔离结构，所述器件隔离结构限定鳍结构的侧壁，其中鳍结构包括布置在 所述衬底和布置在所述缓冲半导体图案上的沟道图案，其中所述缓冲半导体图案具有与所述沟道图案不同的晶格常数，并且其中所述器件隔离结构包括间隙填充绝缘层，并且包括氧化阻挡层 设置在缓冲半导体图案和间隙填充绝缘层之间的图案。

公开(公告)号：US10186460B2

公开(公告)日：2019-01-22

申请号：US15651018

申请日：2017-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu Kim ,  Yunsang Shin

IPC: H01L21/321 ,  H01L21/308 ,  H01L27/092 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02 ,  H01L27/06 ,  H01L29/08

Abstract: A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between adjacent second regions; a plurality of first gate structures on the first regions of the semiconductor substrate; and a plurality of second gate structures on the second regions of the semiconductor substrate, wherein each of the first and second gate structures includes a lower gate structure including a recess region defined by sidewalls and a bottom connecting the sidewalls; and an upper gate structure including a gap-fill metal pattern that fills the recess region of the lower gate structure, wherein the bottom of the lower gate structure included in the first gate structure has a thickness different from a thickness of the bottom of the lower gate structure included in the second gate structure, and wherein the gap-fill metal patterns of the first and second gate structures have top surfaces at substantially a same level.

公开(公告)号：US09502531B2

公开(公告)日：2016-11-22

申请号：US15165931

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，第一区域中包括第一鳍结构和第一栅电极的第一MOS晶体管，第一鳍结构具有第一缓冲图案，第二缓冲图案和 依次层叠在基板上的第一沟道图案和在第二区域中包括第二鳍结构和第二栅电极的第二MOS晶体管，第二鳍结构具有顺序堆叠的第三缓冲图案和第二沟道图案 在基板上。 还讨论了相关的制造方法。

公开(公告)号：US09466601B2

公开(公告)日：2016-10-11

申请号：US14274861

申请日：2014-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region.

Abstract translation: 半导体器件包括包括第一和第二区域的衬底，第一晶体管，设置在第一区域上，以包括从衬底突出的第一沟道区域;以及第二晶体管，设置在第二区域上以包括第二沟道区域和栅电极 在衬底和第二沟道区之间延伸。 第一沟道区可以包括含有与第二沟道区不同的材料的下半导体图案和包含与第二沟道区相同的材料的上半导体图案。

公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。