公开(公告)号：US12183796B2

公开(公告)日：2024-12-31

申请号：US17189615

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbeom Park ,  Sangsu Kim ,  Junggil Yang

IPC: H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

公开(公告)号：US11710739B2

公开(公告)日：2023-07-25

申请号：US17372896

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Minju Kim ,  Donghyi Koh

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

公开(公告)号：US11227952B2

公开(公告)日：2022-01-18

申请号：US16743206

申请日：2020-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Junbeom Park ,  Bongseok Suh ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20210217848A1

公开(公告)日：2021-07-15

申请号：US16943103

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu Kim ,  Junbeom Park ,  Junggil Yang

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

公开(公告)号：US12040326B2

公开(公告)日：2024-07-16

申请号：US18212304

申请日：2023-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Minju Kim ,  Donghyi Koh

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851

Abstract: An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

公开(公告)号：US11699759B2

公开(公告)日：2023-07-11

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Junbeom Park ,  Bongseok Suh ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US11637205B2

公开(公告)日：2023-04-25

申请号：US17140786

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20190165157A1

公开(公告)日：2019-05-30

申请号：US16011785

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  DONG IL BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US09466601B2

公开(公告)日：2016-10-11

申请号：US14274861

申请日：2014-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Sangsu Kim ,  TaeYong Kwon ,  Sung Gi Hur

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region.

Abstract translation: 半导体器件包括包括第一和第二区域的衬底，第一晶体管，设置在第一区域上，以包括从衬底突出的第一沟道区域;以及第二晶体管，设置在第二区域上以包括第二沟道区域和栅电极 在衬底和第二沟道区之间延伸。 第一沟道区可以包括含有与第二沟道区不同的材料的下半导体图案和包含与第二沟道区相同的材料的上半导体图案。

公开(公告)号：US12027523B2

公开(公告)日：2024-07-02

申请号：US17468139

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyun Song ,  Junggil Yang ,  Minju Kim

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/4908 ,  H01L21/28088 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions.