公开(公告)号：US12300629B2

公开(公告)日：2025-05-13

申请号：US18204505

申请日：2023-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/528 ,  H01L23/538 ,  H01L25/18

Abstract: A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

公开(公告)号：US11942437B2

公开(公告)日：2024-03-26

申请号：US18194381

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method includes forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

公开(公告)号：US11621233B2

公开(公告)日：2023-04-04

申请号：US17453225

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park

IPC: H01L23/52 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method inluces forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

公开(公告)号：US10707126B2

公开(公告)日：2020-07-07

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09837429B2

公开(公告)日：2017-12-05

申请号：US15348009

申请日：2016-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/30 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11551

CPC classification number: H01L27/11575 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/34

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US20250155911A1

公开(公告)日：2025-05-15

申请号：US18756948

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaekang Lim ,  Youngwoo Park ,  Seungjin Park ,  Jindo Byun ,  Seunghoon Lee ,  Youngdon Choi

IPC: G05F1/575

Abstract: A voltage regulator includes a pass transistor generating an output voltage in response to a gate voltage, and an error amplifier circuit outputting the gate voltage. The error amplifier circuit includes a first input terminal receiving a first reference voltage level from a reference voltage generator, a second input terminal receiving a second reference voltage level from the reference voltage generator, a third input terminal receiving a first voltage level of a first end of a target circuit, a fourth input terminal receiving a second voltage level of a second end of the target circuit, and an output terminal that outputs the gate voltage generated based on the first reference voltage level, the second reference voltage level, the first voltage level, and the second voltage level. A potential difference of the first voltage level and the second voltage level is an operating voltage of the target circuit.

公开(公告)号：US12229442B2

公开(公告)日：2025-02-18

申请号：US17708771

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngwoo Park ,  Taeduk Nam

IPC: G06F3/06

Abstract: A storage device, including a printed circuit board including a connector including a plurality of pins capable of being coupled to an external host device, a controller socket, a first slot, a second slot, a third slot, and a fourth slot; a first universal flash storage (UFS) device, a second UFS device, a third UFS device, and a fourth UFS device, wherein each UFS device of the first to fourth UFS devices is removably installed in a corresponding slot of the first to fourth slots; and a storage controller mounted in the controller socket, and configured to control the first to fourth UFS devices, wherein the first UFS device and the second UFS device are configured to communicate with the storage controller through a first channel, and the third UFS device and the fourth UFS device are configured to communicate with the storage controller through a second channel.

公开(公告)号：US20210398912A1

公开(公告)日：2021-12-23

申请号：US17171708

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Park

IPC: H01L23/552 ,  H01L25/18 ,  H01L23/528 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

公开(公告)号：US10332902B2

公开(公告)日：2019-06-25

申请号：US15805513

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  G11C16/30 ,  H01L27/11551

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US10032789B2

公开(公告)日：2018-07-24

申请号：US15208669

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Younghwan Son ,  Minyeong Song ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/115 ,  H01L29/167 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.