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公开(公告)号：US20140104923A1
公开(公告)日：2014-04-17
申请号：US14027337
申请日：2013-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ingyu BAEK , Yeong-Taek Lee , KyungMin Kim
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/004
Abstract: Resistive memory driving methods are provided. The methods may include applying an operating voltage set according to a mode of operation to a selected word line among the plurality of word lines and a selected bit line among the plurality of bit lines within a line delay period.
Abstract translation: 提供了电阻式存储器驱动方法。 所述方法可以包括根据操作模式对在多个字线中的所选字线和行延迟周期内的多个位线中的选定位线之间施加设置的工作电压。
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公开(公告)号：US09437290B2
公开(公告)日：2016-09-06
申请号：US14631182
申请日：2015-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Hyo-Jin Kwon , Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
CPC classification number: G11C13/0033 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。
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公开(公告)号：US09111616B2
公开(公告)日：2015-08-18
申请号：US14198608
申请日：2014-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ki-Tae Park , Ki-Nam Kim , Yeong-Taek Lee
CPC classification number: G11C16/0408 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5642
Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.
Abstract translation: 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。
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24.发明授权Nonvolatile memory device using resistance material and method of driving the nonvolatile memory device 有权使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法公开(公告)号：US09082478B2
公开(公告)日：2015-07-14
申请号：US13940856
申请日：2013-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Yeon Lee , Yeong-Taek Lee
CPC classification number: G11C13/004 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2213/71 , G11C2213/72
Abstract: Provided is a nonvolatile memory device using a resistance material and a method of driving the nonvolatile memory device. The nonvolatile memory device comprises a resistive memory cell which stores multiple bits; a sensing node; a clamping unit coupled between the resistive memory cell and the sensing node and provides a clamping bias to the resistive memory cell; a compensation unit which provides a compensation current to the sensing node; a sense amplifier coupled to the sensing node and senses a change in a level of the sensing node; and an encoder which codes an output value of the sense amplifier in response to a first clock signal. The clamping bias varies over time. The compensation current is constant during a read period.
Abstract translation: 提供了使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法。 非易失性存储器件包括存储多个位的电阻存储器单元; 感测节点; 耦合在所述电阻存储器单元和所述感测节点之间的钳位单元，并向所述电阻性存储单元提供钳位偏置; 补偿单元，其向感测节点提供补偿电流; 感测放大器耦合到感测节点并感测感测节点的电平的变化; 以及编码器，其响应于第一时钟信号对读出放大器的输出值进行编码。 钳位偏置随时间而变化。 补偿电流在读取期间是恒定的。
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Patent Agency Ranking
公开(公告)号：US09659645B2
公开(公告)日：2017-05-23
申请号：US14665140
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C13/0023 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2213/71
Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.
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公开(公告)号：US09530494B2
公开(公告)日：2016-12-27
申请号：US14697244
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。
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公开(公告)号：US09183932B1
公开(公告)日：2015-11-10
申请号：US14685671
申请日：2015-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C11/1675 , G11C11/1673 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/72
Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.
Abstract translation: 一种电阻式存储器件，包括布置在第一信号线和第二信号线彼此交叉的区域中的多个电阻性存储器单元，以及操作该电阻式存储器件的方法。 该方法包括从连接到未选择的存储单元的未选择的第一信号线中的第一行应用第一电压，其不与多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线相邻; 从与所选择的第一信号线相邻的未选择的第一信号线中施加低于第一电压的第二电压到第二线; 浮动未选择的第一条信号线; 以及将高于第一电压的第三电压施加到所选择的第一信号线。
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28.发明授权公开(公告)号：US08902633B2
公开(公告)日：2014-12-02
申请号：US13798374
申请日：2013-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Yeon Lee , Yeong-Taek Lee
CPC classification number: G11C13/0069 , G11C7/1006 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C16/3454 , G11C2013/0076 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device comprises a resistive memory cell, a write driver configured to write data to the resistive memory cell during a write period comprising a plurality of loops, and a sense amplifier configured to verify whether the data is correctly written to the resistive memory cell in each of the loops. Where the sense amplifier verifies that the data is correctly written in a k-th loop among the loops, the write driver is disabled from a (k+1)-th loop to an end of the write period.
Abstract translation: 非易失性存储器件包括电阻存储器单元，写入驱动器，配置为在包括多个环路的写入周期期间将数据写入电阻存储器单元;以及读出放大器，其被配置为验证数据是否被正确写入电阻存储器单元 在每个循环中。 在感测放大器验证数据在循环中的第k个循环中被正确地写入的情况下，写入驱动器被禁止从第（k + 1）个循环到写周期的结束。
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29.发明申请公开(公告)号：US20140211538A1
公开(公告)日：2014-07-31
申请号：US13798374
申请日：2013-03-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Yeon Lee , Yeong-Taek Lee
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C7/1006 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C16/3454 , G11C2013/0076 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device comprises a resistive memory cell, a write driver configured to write data to the resistive memory cell during a write period comprising a plurality of loops, and a sense amplifier configured to verify whether the data is correctly written to the resistive memory cell in each of the loops. Where the sense amplifier verifies that the data is correctly written in a k-th loop among the loops, the write driver is disabled from a (k+1)-th loop to an end of the write period.
Abstract translation: 非易失性存储器件包括电阻存储器单元，写入驱动器，配置为在包括多个环路的写入周期期间将数据写入电阻存储器单元;以及读出放大器，其被配置为验证数据是否被正确写入电阻存储器单元 在每个循环中。 在感测放大器验证数据在循环中的第k个循环中被正确地写入的情况下，写入驱动器被禁止从第（k + 1）个循环到写周期的结束。
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