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    Vertical memory devices
    21.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11895838B2

    公开(公告)日：2024-02-06

    申请号：US17158107

    申请日：2021-01-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokcheon Baek

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: A vertical memory device includes a first gate structure on a substrate, the first gate structure including first gate electrodes spaced from each other in a first direction and stacked in a staircase shape, a second gate structure on the first gate structure and including second gate electrodes spaced from each other in the first direction and stacked in the staircase shape, a channel extending through the first and second gate structures, and a contact plug extending in the first direction through the first and second gate structures, wherein second steps at end portions of the second gate electrodes overlap first steps at end portions of the first gate electrodes, and wherein the contact plug extends through at least one of the first steps and through at least one of the second steps, while being electrically connected only to the first steps or to the second steps.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    22.
    发明公开
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230378095A1

    公开(公告)日：2023-11-23

    申请号：US18227908

    申请日：2023-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yujin Kwon ,  Seokcheon Baek ,  Younghwan Son

    IPC: H01L23/00 ,  H01L23/528 ,  H01L25/18

    CPC classification number: H01L23/562 ,  H01L23/528 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08146 ,  H10B41/27

    Abstract: A semiconductor device includes first and second gate electrodes stacked and spaced apart from each other in a first direction on a first region of a substrate, and extending in staircase form in a second direction on a second region of the substrate, the second gate electrodes disposed on the first gate electrodes; a first support structure penetrating the first gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level lower than a level of a lowermost second gate electrode among the second gate electrodes; a second support structure penetrating at least one of the first and second gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level higher than a level of un uppermost second gate electrode among the second gate electrodes.

    Semiconductor devices including stack structure having gate region and insulating region
    23.
    发明授权
    Semiconductor devices including stack structure having gate region and insulating region 有权

    公开(公告)号：US11744066B2

    公开(公告)日：2023-08-29

    申请号：US17685692

    申请日：2022-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwon Lim ,  Seokcheon Baek

    IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

    CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/788

    Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

    Three-dimensional semiconductor memory devices
    25.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10665606B2

    公开(公告)日：2020-05-26

    申请号：US16222059

    申请日：2018-12-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon Baek ,  Geunwon Lim ,  Hwan Lee

    IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/105

    Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME
    26.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING SAME 审中-公开

    公开(公告)号：US20170301688A1

    公开(公告)日：2017-10-19

    申请号：US15613602

    申请日：2017-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woong-Seop Lee ,  Seokcheon Baek ,  Jinhyun Shin

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11575

    Abstract: A vertical NAND-type memory device includes a vertical stack of inter-gate insulating layers and gate electrodes arranged in an alternating sequence on an underlying substrate, which includes a cell array region and a contact region therein. At least one NAND-type channel structure is provided, which extends vertically through the vertical stack of inter-gate insulating layers and gate electrodes. An end sidewall of a first of the gate electrodes, which extends laterally over at least a portion of the contact region, has a vertical slope that is less steep than vertical slopes of end sidewalls of a first plurality of the gate electrodes extending between the first of the gate electrodes and the substrate.

    Semiconductor devices and data storage systems including the same
    27.
    发明授权
    Semiconductor devices and data storage systems including the same 有权

    公开(公告)号：US12120876B2

    公开(公告)日：2024-10-15

    申请号：US17679268

    申请日：2022-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon Baek ,  Miram Kwon ,  Seongjun Seo ,  Younghwan Son

    IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H01L27/0688 ,  H10B43/40

    Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

    Vertical memory devices
    29.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US12048152B2

    公开(公告)日：2024-07-23

    申请号：US17035930

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokcheon Baek

    IPC: H01L27/11582 ,  G11C8/14 ,  H01L23/522 ,  H01L27/11565 ,  H01L29/423 ,  H01L29/792 ,  H10B43/10 ,  H10B43/27

    CPC classification number: H10B43/27 ,  G11C8/14 ,  H01L23/5226 ,  H01L29/4234 ,  H01L29/7926 ,  H10B43/10

    Abstract: A vertical memory device includes a plurality of memory blocks having a plurality of horizontal gate electrodes spaced apart from each other in a first direction and extending in a second direction. A plurality of vertical channels extends through the horizontal gate electrodes in the first direction. A plurality of charge storage structures are disposed between the vertical channels and the horizontal gate electrodes. A conductive path extends in a third direction. The plurality of memory blocks are arranged in the third direction and are divided from each other by a first division pattern that extends in the second direction. The plurality of horizontal gate electrodes at each level are connected to the conductive path at a first lateral side in the second direction to form a shared memory block.

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