公开(公告)号：US20180076127A1

公开(公告)日：2018-03-15

申请号：US15816243

申请日：2017-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US09576848B2

公开(公告)日：2017-02-21

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US09524937B2

公开(公告)日：2016-12-20

申请号：US14503877

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括导电图案之间的间隙。 此外，半导体器件在导电图案上包括可渗透层。 还提供了制造半导体器件的方法。

公开(公告)号：US20240411227A1

公开(公告)日：2024-12-12

申请号：US18427044

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gap Im ,  Seonkyu Shin ,  Sanghoon Ahn ,  Hanhum Park ,  Minkyung Cho ,  Chungryeol Lee ,  Seungmin Lee ,  Changhyeon Lee ,  Sukwon Jang

IPC: G03F7/11 ,  G03F7/031 ,  G03F7/16 ,  H01L21/027 ,  H01L21/308

Abstract: A photolithograph method is provided. The photolithograph method may include forming a photoresist pattern on a substrate and conformally forming a liner layer on the photoresist pattern, wherein the forming of the liner layer includes a deposition process of reacting an initiator and a monomer with each other, the monomer includes multiple bonds between carbon atoms, the initiator includes a material that forms a radical by thermal decomposition, a copolymer is formed by an initiating reaction between the radical and the monomer, and the liner layer includes the copolymer.

公开(公告)号：US12125785B2

公开(公告)日：2024-10-22

申请号：US17530206

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Jongmin Baek ,  Sanghoon Ahn ,  Woojin Lee ,  Junhyuk Lim

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53257

Abstract: A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

公开(公告)号：US12080595B2

公开(公告)日：2024-09-03

申请号：US17411467

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Sanghoon Ahn ,  Woojin Lee ,  Kyung-Eun Byun ,  Junghoo Shin ,  Hyeonjin Shin ,  Yunseong Lee

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/7685 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/28562

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US11862514B2

公开(公告)日：2024-01-02

申请号：US17984874

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Ahn ,  Woojin Lee ,  Kyuhee Han

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00 ,  H01L23/48 ,  H01L23/28

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/76895 ,  H01L23/28 ,  H01L23/48 ,  H10B12/482

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

公开(公告)号：US11569128B2

公开(公告)日：2023-01-31

申请号：US17174409

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

IPC: H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US20220238433A1

公开(公告)日：2022-07-28

申请号：US17453197

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Sanghoon Ahn ,  Seung Jae Lee ,  Deokyoung Jung ,  Woojin Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.

公开(公告)号：US10269712B2

公开(公告)日：2019-04-23

申请号：US15927270

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.