公开(公告)号：US11069613B2

公开(公告)日：2021-07-20

申请号：US16742233

申请日：2020-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Junghoo Shin ,  Sanghoon Ahn ,  Junhyuk Lim ,  Daehan Kim

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/485

Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

公开(公告)号：US11721622B2

公开(公告)日：2023-08-08

申请号：US17453197

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Sanghoon Ahn ,  Seung Jae Lee ,  Deokyoung Jung ,  Woojin Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53204

Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.

公开(公告)号：US20240162323A1

公开(公告)日：2024-05-16

申请号：US18489220

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoo Shin ,  Sangcheol Na ,  Minjae Kang ,  Yongjin Kwon ,  Soeun Kim ,  Jongmin Baek

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: The integrated circuit device includes a substrate, a first fin extending in a first horizontal direction on the substrate, a second fin and a third fin spaced apart from each other in the first horizontal direction and extending in the first horizontal direction, a second source/drain area on the second fin and the third fin, a back side contact between the second fin and the third fin and electrically connected to the second source/drain area, and a back side conductive layer extending in the first horizontal direction and electrically connected to the back side contact. The back side contact includes a first portion protruding from the substrate and a second portion that is coplanar, in a vertical direction, with the substrate. A width of the second portion in the second horizontal direction is greater than a width of the first portion in the second horizontal direction.

公开(公告)号：US12125785B2

公开(公告)日：2024-10-22

申请号：US17530206

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Jongmin Baek ,  Sanghoon Ahn ,  Woojin Lee ,  Junhyuk Lim

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53257

Abstract: A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

公开(公告)号：US12080595B2

公开(公告)日：2024-09-03

申请号：US17411467

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Sanghoon Ahn ,  Woojin Lee ,  Kyung-Eun Byun ,  Junghoo Shin ,  Hyeonjin Shin ,  Yunseong Lee

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/7685 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/28562

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20220238433A1

公开(公告)日：2022-07-28

申请号：US17453197

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Sanghoon Ahn ,  Seung Jae Lee ,  Deokyoung Jung ,  Woojin Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.