公开(公告)号：US09281277B2

公开(公告)日：2016-03-08

申请号：US14527842

申请日：2014-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Baek ,  Sang-Ho Rha ,  Woo-Kyung You ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Ki-Chul Kim ,  Jeon-Il Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Abstract translation: 布线结构包括第一绝缘层，多个布线图案，保护层图案和第二绝缘层。 第一绝缘层可以形成在基板上。 可以在第一绝缘层上形成多个布线图案，并且每个布线图案可以包括覆盖金属层图案的侧壁和底表面的金属层图案和阻挡层图案。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。

公开(公告)号：US20150194333A1

公开(公告)日：2015-07-09

申请号：US14516774

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Kyung You ,  Sang-Ho Rha ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76877

Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.

Abstract translation: 提供形成布线结构的方法包括在基板上形成绝缘中间层并在绝缘中间层上形成牺牲层。 牺牲层被部分地去除以限定多个开口。 在开口中形成接线图案。 通过等离子体处理将牺牲层转变成改性的牺牲层。 通过湿蚀刻工艺去除改性牺牲层。 在绝缘中间层上形成覆盖布线图案的绝缘层。 绝缘层在相邻布线图案之间限定了气隙。

公开(公告)号：US11600569B2

公开(公告)日：2023-03-07

申请号：US17230509

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Hyun Bark ,  Sang-Hoon Ahn ,  Young-Bae Kim ,  Hyeok-Sang Oh ,  Woo-Jin Lee ,  Hoon-Seok Seo ,  Sung-Jin Kang

IPC: H01L23/48 ,  H01L23/532 ,  H01L29/16 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8234

Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

公开(公告)号：US10529618B2

公开(公告)日：2020-01-07

申请号：US15870175

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siqing Lu ,  Sang-Hoon Ahn ,  Xinglong Chen ,  Ki-Hyun Kim ,  Kyu-In Shim

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L21/027 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.

公开(公告)号：US10008407B2

公开(公告)日：2018-06-26

申请号：US14955988

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd

Inventor： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

公开(公告)号：US09929098B2

公开(公告)日：2018-03-27

申请号：US15048998

申请日：2016-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Yim ,  Sang-Hoon Ahn ,  Thomas Oszinda ,  Jong-Min Baek ,  Byung Hee Kim ,  Nae-In Lee ,  Kee-Young Jun

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53295

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

公开(公告)号：US09793347B2

公开(公告)日：2017-10-17

申请号：US14931427

申请日：2015-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Jin Lee ,  Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Won Hong

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76831

Abstract: A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.

公开(公告)号：US09728604B2

公开(公告)日：2017-08-08

申请号：US15059438

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US09633836B2

公开(公告)日：2017-04-25

申请号：US14291670

申请日：2014-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Seung-Hyuk Choi ,  Kyu-Hee Han

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

公开(公告)号：US20160133577A1

公开(公告)日：2016-05-12

申请号：US15000282

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Baek ,  Sang-Ho Rha ,  Woo-Kyung You ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Ki-Chul Kim ,  Jeon-Il Lee

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Abstract translation: 布线结构包括第一绝缘层，多个布线图案，保护层图案和第二绝缘层。 第一绝缘层可以形成在基板上。 可以在第一绝缘层上形成多个布线图案，并且每个布线图案可以包括覆盖金属层图案的侧壁和底表面的金属层图案和阻挡层图案。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。 保护层图案可以覆盖每个布线图案的顶表面，并且包括相对于氧具有高反应性的材料。