公开(公告)号：US09728604B2

公开(公告)日：2017-08-08

申请号：US15059438

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10332791B2

公开(公告)日：2019-06-25

申请号：US15805865

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yun Jeon ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Kyoung-Hee Nam ,  Jong-Jin Lee ,  Jae-Won Hwang

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288 ,  H01L23/528 ,  H01L23/522 ,  H01L21/285

Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

公开(公告)号：US20190189744A1

公开(公告)日：2019-06-20

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L27/12 ,  H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10217820B2

公开(公告)日：2019-02-26

申请号：US15632884

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US10700164B2

公开(公告)日：2020-06-30

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20180158730A1

公开(公告)日：2018-06-07

申请号：US15805865

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Yun Jeon ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Kyoung-Hee Nam ,  Jong-Jin Lee ,  Jae-Won Hwang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76865 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238

Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

公开(公告)号：US20170294337A1

公开(公告)日：2017-10-12

申请号：US15632884

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam KIM ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20160300792A1

公开(公告)日：2016-10-13

申请号：US15059438

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam KIM ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51 ,  H01L29/16 ,  H01L29/161 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract translation: 半导体器件可以包括扩散防止绝缘图案，多个导电图案，阻挡层和绝缘中间层。 扩散防止绝缘图案可以形成在基板上，并且可以包括从其向上突出的多个突起。 每个导电图案可以形成在防扩散绝缘图案的每个突起上，并且可以具有相对于基板的顶表面倾斜约80度至约135度范围内的角度的侧壁。 如果导电图案，阻挡层可以覆盖每个的顶表面和侧壁。 绝缘中间层可以形成在防扩散绝缘图案和阻挡层上，并且可以在相邻的导电图案之间具有气隙。