公开(公告)号：US20240012045A1

公开(公告)日：2024-01-11

申请号：US18471624

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahn Choi ,  Reum Oh

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/2884 ,  G01R31/318511 ,  G01R31/31715

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

公开(公告)号：US11829224B2

公开(公告)日：2023-11-28

申请号：US17742175

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyeon Park ,  Youngjae Park ,  Hyungjin Kim ,  Reum Oh ,  Jinyong Choi

IPC: G06F1/00 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3203

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F1/3203

Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.

公开(公告)号：US20220357393A1

公开(公告)日：2022-11-10

申请号：US17872440

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahn Choi ,  Reum Oh

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/317

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

公开(公告)号：US11334282B2

公开(公告)日：2022-05-17

申请号：US17173779

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

公开(公告)号：US10768824B2

公开(公告)日：2020-09-08

申请号：US16418502

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

公开(公告)号：US10224114B2

公开(公告)日：2019-03-05

申请号：US15600715

申请日：2017-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Ryu ,  Hak-soo Yu ,  Reum Oh ,  Seong-young Seo ,  Soo-jung Rho

IPC: G11C29/12 ,  G11C5/00 ,  G11C29/26 ,  G11C29/54

Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

公开(公告)号：US12250807B2

公开(公告)日：2025-03-11

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H10B12/00 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US11681457B2

公开(公告)日：2023-06-20

申请号：US17728107

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C7/00 ,  G11C5/04 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0653 ,  G06F3/0655 ,  G06F12/0292 ,  G06F13/1694 ,  G11C7/1057 ,  G11C7/1084

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

公开(公告)号：US11435397B2

公开(公告)日：2022-09-06

申请号：US16665318

申请日：2019-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahn Choi ,  Reum Oh

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/317

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

公开(公告)号：US10996885B2

公开(公告)日：2021-05-04

申请号：US16208989

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Gyu Lee ,  Reum Oh ,  Ki Heung Kim ,  Moon Hee Oh

IPC: G11C5/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.