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    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE
    4.
    发明申请
    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE 有权

    公开(公告)号：US20210335413A1

    公开(公告)日：2021-10-28

    申请号：US17369010

    申请日：2021-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O ,  Hak-soo Yu

    IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

    Method of performing internal processing operation of memory device
    5.
    发明授权
    Method of performing internal processing operation of memory device 有权

    公开(公告)号：US11074961B2

    公开(公告)日：2021-07-27

    申请号：US16251983

    申请日：2019-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Pavan Kumar Kasibhatla ,  Seong-il O ,  Hak-soo Yu

    IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

    Memory device with internal processing interface
    8.
    发明授权
    Memory device with internal processing interface 有权

    公开(公告)号：US12099455B2

    公开(公告)日：2024-09-24

    申请号：US17591928

    申请日：2022-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hak-soo Yu ,  Shinhaeng Kang ,  Yuhwan Ro

    IPC: G06F13/16 ,  G06F9/30 ,  G06F13/38 ,  G06F13/40 ,  G06F15/78 ,  G11C7/18 ,  G11C8/14

    CPC classification number: G06F13/1668 ,  G06F9/3016

    Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
    9.
    发明授权
    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US08730710B2

    公开(公告)日：2014-05-20

    申请号：US14017856

    申请日：2013-09-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    IPC: G11C11/00

    CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE
    10.
    发明申请
    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE 有权

    公开(公告)号：US20220383938A1

    公开(公告)日：2022-12-01

    申请号：US17883498

    申请日：2022-08-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Pavan Kumar KASIBHATLA ,  Seong-Il O ,  Hak-soo Yu

    IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

    Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

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