公开(公告)号：US10684793B2

公开(公告)日：2020-06-16

申请号：US15462347

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-ju Chung ,  Su-a Kim ,  Mu-jin Seo ,  Hak-soo Yu ,  Jae-youn Youn ,  Hyo-jin Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G06F11/07 ,  G11C11/409 ,  G11C29/00 ,  G11C29/52

Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.