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    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device
    1.
    发明授权
    Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory controller and memory system using the memory device 有权
    具有根据温度的放松定时参数的存储器件，其操作方法以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US09465757B2

    公开(公告)日：2016-10-11

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F12/02 ,  G06F13/16 ,  G11C11/406

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE 有权
    具有根据温度的放松时序参数的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统

    公开(公告)号：US20140359242A1

    公开(公告)日：2014-12-04

    申请号：US14290997

    申请日：2014-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-pil Son ,  Uk-song Kang ,  Chul-woo Park ,  Seong-young Seo

    IPC: G06F13/16

    CPC classification number: G06F13/1689 ,  G11C7/04 ,  G11C7/1045 ,  G11C11/40626 ,  G11C11/4076

    Abstract: A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device.

    Abstract translation: 提供了一种根据温度的轻松的时序要求规范使用的存储器件，其操作方法，以及使用存储器件的存储器控​​制器和存储器系统。 存储装置在第一温度下具有第一定时特性，在第二温度下具有长于第一定时特性的第二定时特性。 如果存储器件的温度高于参考温度，则存储器控制器控制第一定时特性作为存储器件的定时要求指定。 如果存储器件的温度低于参考温度，则存储器控制器控制第二定时特性作为存储器件的定时要求规范。

    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
    3.
    发明授权
    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US08730710B2

    公开(公告)日：2014-05-20

    申请号：US14017856

    申请日：2013-09-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    IPC: G11C11/00

    CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

    Memory device that performs internal copy operation
    5.
    发明授权
    Memory device that performs internal copy operation 有权

    公开(公告)号：US10983792B2

    公开(公告)日：2021-04-20

    申请号：US16189642

    申请日：2018-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-soo Sohn ,  Sei-jin Kim ,  Kwang-il Park ,  Tae-young Kim ,  Chul-woo Park

    IPC: G06F12/00 ,  G06F9/30 ,  G06F15/78

    Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US20140008598A1

    公开(公告)日：2014-01-09

    申请号：US14017856

    申请日：2013-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    IPC: H01L45/00

    CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

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