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公开(公告)号:US20170069371A1
公开(公告)日:2017-03-09
申请号:US15258174
申请日:2016-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-jun Shin , Tae-young Oh , Kwang-il Park
IPC: G11C11/406
CPC classification number: G11C11/40615
Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.
Abstract translation: 刷新存储器件的方法包括响应于刷新命令对存储器单元行执行正常刷新操作,并且在存储器的自刷新模式期间响应于刷新时钟信号对存储器单元行执行自刷新操作 设备在自刷新输入命令和自刷新退出命令之间。 刷新时钟信号在自刷新开始之前具有第一自刷新周期,并且在自刷新开始之后具有可能比第一自刷新周期长的第二自刷新周期。 在一些示例中,在自刷新模式期间,存储器件不能执行自刷新。
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公开(公告)号:US09875155B2
公开(公告)日:2018-01-23
申请号:US15371876
申请日:2016-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
CPC classification number: G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
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公开(公告)号:US09767882B2
公开(公告)日:2017-09-19
申请号:US15258174
申请日:2016-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-jun Shin , Tae-young Oh , Kwang-il Park
IPC: G11C7/00 , G11C11/406
CPC classification number: G11C11/40615
Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.
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公开(公告)号:US20220198111A1
公开(公告)日:2022-06-23
申请号:US17692883
申请日:2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.
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公开(公告)号:US11281832B2
公开(公告)日:2022-03-22
申请号:US16788924
申请日:2020-02-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.
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公开(公告)号:US20170097790A1
公开(公告)日:2017-04-06
申请号:US15194963
申请日:2016-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Su-yeon Doo , Tae-young Oh , Kwang-il Park
CPC classification number: G06F13/1668 , G06F3/061 , G06F3/0635 , G06F3/0659 , G06F3/0688
Abstract: A memory module includes a first memory group including a plurality of first semiconductor memory devices, and a second memory group including a plurality of second semiconductor memory devices. The first semiconductor memory devices and the second semiconductor memory devices share a command/address bus. The first semiconductor memory devices perform a first operation in response to a command signal received by the first semiconductor memory devices from the command/address bus and the second semiconductor memory devices perform a second operation, different from the first operation, in response to the same command signal received by the second semiconductor memory devices from the command/address bus.
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公开(公告)号:US11861280B2
公开(公告)日:2024-01-02
申请号:US17692883
申请日:2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.
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公开(公告)号:US10388399B2
公开(公告)日:2019-08-20
申请号:US15850152
申请日:2017-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hye-jung Kwon , Kwang-il Park , Seung-jun Bae , Eun-sung Seo
Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.
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公开(公告)号:US08854916B2
公开(公告)日:2014-10-07
申请号:US13862957
申请日:2013-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
IPC: G11C8/00 , G11C8/18 , G11C11/4076 , G11C8/12 , G11C7/08 , G11C11/4091
CPC classification number: G11C8/18 , G11C7/08 , G11C8/12 , G11C11/4076 , G11C11/4091
Abstract: Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.
Abstract translation: 示例性实施例提供半导体存储器件,其可以包括:布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间,对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。
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公开(公告)号:US10983792B2
公开(公告)日:2021-04-20
申请号:US16189642
申请日:2018-11-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young-soo Sohn , Sei-jin Kim , Kwang-il Park , Tae-young Kim , Chul-woo Park
Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.
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