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    MEMORY DEVICE HAVING A PLURALITY OF LOW POWER STATES
    2.
    发明申请
    MEMORY DEVICE HAVING A PLURALITY OF LOW POWER STATES 有权

    公开(公告)号：US20230004313A1

    公开(公告)日：2023-01-05

    申请号：US17903589

    申请日：2022-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeon-kyu CHOI ,  Ki-seok Oh ,  Seung-jun Shin ,  Hye-ran Kim

    IPC: G06F3/06 ,  G11C11/4074 ,  G11C11/406

    Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

    METHOD OF REFRESHING MEMORY DEVICE
    3.
    发明申请
    METHOD OF REFRESHING MEMORY DEVICE 有权
    刷新存储器件的方法

    公开(公告)号：US20170069371A1

    公开(公告)日：2017-03-09

    申请号：US15258174

    申请日：2016-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-jun Shin ,  Tae-young Oh ,  Kwang-il Park

    IPC: G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

    Abstract translation: 刷新存储器件的方法包括响应于刷新命令对存储器单元行执行正常刷新操作，并且在存储器的自刷新模式期间响应于刷新时钟信号对存储器单元行执行自刷新操作 设备在自刷新输入命令和自刷新退出命令之间。 刷新时钟信号在自刷新开始之前具有第一自刷新周期，并且在自刷新开始之后具有可能比第一自刷新周期长的第二自刷新周期。 在一些示例中，在自刷新模式期间，存储器件不能执行自刷新。

    Memory device configured to store and output address in response to internal command
    4.
    发明授权
    Memory device configured to store and output address in response to internal command 审中-公开

    公开(公告)号：US10671319B2

    公开(公告)日：2020-06-02

    申请号：US16010814

    申请日：2018-06-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung-jun Shin ,  Hyong-ryol Hwang

    IPC: G06F3/06 ,  G11C7/10 ,  G06F12/06 ,  G11C8/18

    Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.

    Method of refreshing memory device
    8.
    发明授权
    Method of refreshing memory device 有权

    公开(公告)号：US09767882B2

    公开(公告)日：2017-09-19

    申请号：US15258174

    申请日：2016-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-jun Shin ,  Tae-young Oh ,  Kwang-il Park

    IPC: G11C7/00 ,  G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

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