公开(公告)号：US20180121124A1

公开(公告)日：2018-05-03

申请号：US15797525

申请日：2017-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-kyu CHOI ,  Ki-seok OH ,  Seung-jun SHIN ,  Hye-ran KIM

IPC: G06F3/06 ,  G11C11/406

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

公开(公告)号：US20230004313A1

公开(公告)日：2023-01-05

申请号：US17903589

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-kyu CHOI ,  Ki-seok Oh ,  Seung-jun Shin ,  Hye-ran Kim

IPC: G06F3/06 ,  G11C11/4074 ,  G11C11/406

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

公开(公告)号：US20220413725A1

公开(公告)日：2022-12-29

申请号：US17903540

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-kyu CHOI ,  Ki-seok OH ,  Seung-jun SHIN ,  Hye-ran KIM

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/4074

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.