公开(公告)号：US11282555B2

公开(公告)日：2022-03-22

申请号：US17190656

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US08854916B2

公开(公告)日：2014-10-07

申请号：US13862957

申请日：2013-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC: G11C8/00 ,  G11C8/18 ,  G11C11/4076 ,  G11C8/12 ,  G11C7/08 ,  G11C11/4091

CPC classification number: G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

Abstract: Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

Abstract translation: 示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

公开(公告)号：US20180102151A1

公开(公告)日：2018-04-12

申请号：US15723532

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G11C7/22 ,  G06F13/16 ,  G06F1/12 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US09754650B2

公开(公告)日：2017-09-05

申请号：US15187967

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Tae-Young Oh

IPC: G11C7/22 ,  G11C7/12

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/12 ,  G11C2207/2254

Abstract: A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.

公开(公告)号：US09898438B2

公开(公告)日：2018-02-20

申请号：US14879618

申请日：2015-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Tae-Young Oh

IPC: G06F3/06 ,  G06F13/42

CPC classification number: G06F13/4243

Abstract: A memory system includes a transmitter and a receiver. The transmitter is configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface. The data burst includes a first data and a subsequent data. The receiver is configured to receive the data signal, to detect the first symbol lock pattern based on the received data signal, and to find the first data of the data burst according to the detected first symbol lock pattern.

公开(公告)号：US09711192B2

公开(公告)日：2017-07-18

申请号：US14931291

申请日：2015-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Tae-Young Oh ,  Seong-Jin Jang

IPC: G11C5/14 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C5/147 ,  G11C5/148 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/12 ,  G11C2207/2227

Abstract: A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.

公开(公告)号：US12057193B2

公开(公告)日：2024-08-06

申请号：US18111925

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/222 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US12020738B2

公开(公告)日：2024-06-25

申请号：US17536537

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Seok Kang ,  Sun Young Kim ,  Hye-Ran Kim ,  Tae-Yoon Lee ,  Sung Yong Cho

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G11C11/406 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

公开(公告)号：US20240005204A1

公开(公告)日：2024-01-04

申请号：US18054176

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiwon Lee ,  Sung-Rae Kim ,  Gilyoung Kang ,  Hye-Ran Kim ,  Chisung Oh

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: A semiconductor device includes a sequence data generator, which is configured to generate sequence data on a plurality of data lines, and a symbol changer. The symbol changer is configured to generate a training pattern from the sequence data by replacing, for each of the plurality of data lines, each occurrence of a bitstream within the sequence data that has a predetermined symbol with an alternative symbol. The sequence data generator may include a sequence generator, which is configured to generate a pseudo random binary sequence (PRBS), based on a seed value for each clock cycle.

公开(公告)号：US11615825B2

公开(公告)日：2023-03-28

申请号：US17588566

申请日：2022-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.